Level Epsilon Architecture Support Reference Manual

ClearPath Enterprise Servers 

Level Epsilon 

Architecture Support Reference Manual 

September 2012 6878 7530–007 

unisys

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Contents 

Section 1. Introduction 

Purpose ................................................................................................. 1–1 

Scope .................................................................................................... 1–1 

Audience ............................................................................................... 1–1 

Prerequisites ......................................................................................... 1–1 

Documentation Updates ....................................................................... 1–1 

Section 2. Process Model 

Addressing Granularity: Words ............................................................. 2–1 

Segments and Descriptors ................................................................... 2–1 

Actual Segments and Actual Segment Descriptors 

(ASDs) ............................................................................. 2–2 

Virtual Segments and Virtual Segment Descriptors 

(DDs and CSDs) ............................................................... 2–2 

Procedures: Activation Records ............................................................ 2–3 

Processes: Stacks ................................................................................. 2–4 

Programs: Code Segment Dictionaries ................................................. 2–4 

Linkages and Addressing Environments ............................................... 2–5 

References ............................................................................................ 2–6 

Protection .............................................................................................. 2–7 

Accessing Segments ........................................................... 2–7 

Access Control..................................................................... 2–8 

Addressing ............................................................................................ 2–9 

Procedure Entry/Exit ............................................................................. 2–9 

Expression Stack and Stack Frames ................................................... 2–10 

Stack and Display Registers ................................................................ 2–11 

Executable Code Streams ................................................................... 2–11 

General Boolean Accumulators........................................................... 2–12 

ASD Memory Architecture .................................................................. 2–12 

Section 3. Data Structure and Text 

Word Format ......................................................................................... 3–1 

Data Words ........................................................................................... 3–2 

Operands (Single and Double Precision) ............................. 3–2 

Tag-4 Word and Tag-6 Word ................................................ 3–5 

Program Code Words ........................................................................... 3–5 

Actual Segment Descriptors (ASD) ....................................................... 3–5 

Actual Segment Descriptor, First Word (ASD1) .................. 3–6 

Actual Segment Descriptor, Second Word (ASD2) ............. 3–6 

Absolute Store Reference Word (ASRW) ............................................. 3–7 

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Contents 

Section 4. Interrupts 

Virtual Segment Descriptor (VSD) ......................................................... 3–7 

Untouched DD ...................................................................... 3–7 

Unindexed (Original and Copy) DD ....................................... 3–7 

IndexedDD (Indexed Data Descriptor .................................. 3–8 

Code Segment Descriptor (CSD) ......................................... 3–9 

Virtual Segments ................................................................................. 3–10 

Virtual Index ......................................................................................... 3–11 

References .......................................................................................... 3–12 

Address Couples ................................................................ 3–12 

Environment Links .............................................................. 3–13 

Stuffed Indirect Reference Word (SIRW) ........................... 3–14 

Program Control Word (PCW) ............................................ 3–14 

Stack Structure and Linkage ................................................................ 3–15 

Stack Frame Linkage .......................................................... 3–16 

Top-of-Stack Linkage .......................................................... 3–17 

Protected Object Word (POW) ............................................................ 3–18 

Tag Values ........................................................................................... 3–19 

Data Structure Access ......................................................................... 3–20 

Interrupt Mechanism ............................................................................. 4–1 

Superhalt .............................................................................. 4–1 

Interrupt References ............................................................ 4–2 

Vector Interrupt Formats ...................................................... 4–2 

Code Stream Designation and Resumption ......................... 4–3 

Interrupt Parameters ............................................................ 4–4 

Restart Configuration ........................................................... 4–5 

Operator Subdivision ............................................................ 4–5 

Interrupt Definition ................................................................................. 4–6 

Arithmetic Interrupts ............................................................ 4–7 

Service Interrupts ............................................................... 4–10 

Enforcement Interrupts ...................................................... 4–14 

Alarm Interrupts (Libra 6xx and 7xx Systems) ................... 4–22 

Asynchronous Interrupts .................................................... 4–26 

External Interrupts .............................................................. 4–27 

Maskable External Interrupts ............................................. 4–28 

Interrupt Vector .................................................................................... 4–29 

Section 5. Operator Set 

General Information ............................................................................... 5–1 

Operators and Code Streams ............................................... 5–1 

Interrupts and Resumption .................................................. 5–3 

Operator Applicability ........................................................... 5–4 

Expression Stack Control ..................................................... 5–5 

Stack-State Transformation .................................................. 5–6 

Expression Stack Treatment of Word Extension ................. 5–7 

Descriptor Interpretation ...................................................... 5–7 

Computational Operators ...................................................................... 5–8 

Numeric Operand Interpretation .......................................... 5–8 

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Numeric-Interpretation Operators ..................................... 5–19 

Bit Vector Interpretation .................................................... 5–29 

Linear Index-Function Operator ......................................... 5–39 

Reference Generation and Evaluation Operators ............................... 5–41 

Double Precision ................................................................ 5–41 

Stack References .............................................................. 5–41 

Environment Link Evaluation ............................................. 5–41 

Evaluation of References ................................................... 5–41 

Reference Generation Operators ...................................... 5–44 

Reference Modification Operators .................................... 5–50 

Descriptor Attribute Extraction Operators ......................... 5–51 

Read Evaluation Operators ................................................ 5–52 

Normal Store Operators .................................................... 5–59 

Overwrite Operators .......................................................... 5–61 

Character Reference Evaluation Operators ....................... 5–63 

Processor State Operators .................................................................. 5–65 

Code Stream Pointer Distribution ...................................... 5–65 

Branching Operators .......................................................... 5–65 

Stack Frame Operators ...................................................... 5–67 

Assertion Operators .......................................................... 5–73 

Top-Of-Stack Operators ..................................................... 5–73 

Processor-State Manipulation Operators .......................... 5–75 

Data Array Operators .......................................................................... 5–77 

Paged Array Operations ..................................................... 5–77 

Searching Operators .......................................................... 5–78 

Pointer Operators .............................................................. 5–80 

Vector Operators ............................................................. 5–109 

Miscellaneous Operators .................................................................. 5–121 

Program Restrictions Due to Hidden State ....................................... 5–122 

Section 6. Restricted Operators 

Restricted General Operators ............................................................... 6–1 

Restricted Reference Operators.......................................... 6–1 

Program Restrictions Due to Hidden State ......................... 6–3 

Restricted Processor State Operators ................................. 6–4 

Restricted Task Control Operators ...................................... 6–8 

Restricted Time of Day Operators ..................................... 6–10 

Restricted Platform Operators ............................................................ 6–11 

Restricted Memory Access Functions .............................. 6–11 

Restricted System Interrupt Functions ............................. 6–15 

Restricted Time of Day Functions (Libra 6xx and 

7xx Systems) ................................................................. 6–21 

Time Management (Libra 4000 System) ........................... 6–23 

System-Specific Platform Support Operator ..................... 6–26 

Restricted I/O Support Operator........................................ 6–27 

Restricted Word Extension Operators ................................................ 6–28 

Appendix A. Alphabetical Operator Code List 

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Contents 

Appendix B. Boolean Accumulator X-Ref 

TFFF (true/false flip-flop) ....................................................................... B–1 

OFFF (overflow flip-flop) ....................................................................... B–2 

EXTF (external sign flip-flop) ................................................................. B–2 

FLTF (float flip-flop) ............................................................................... B–2 

TFFF, OFFF, and EXTF .......................................................................... B–3 

FLTF ...................................................................................................... B–3 

Appendix C. Operator Encoding 

Primary Mode Operators ...................................................................... C–2 

Variant Mode Operators ....................................................................... C–4 

Edit Mode Operators ............................................................................ C–6 

Appendix D. Data Type Formats 

Appendix E. Processor Features Operators 

Appendix F. Operator and Common Action Reference 

Appendix G. Interupt Reference 

Index ............................................................................................. 1 

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6878 7530–007 vii

Contents 

viii 6878 7530–007

Section 1 

Introduction 

Purpose 

Scope 

Audience 

This manual describes the system concepts needed as background to understand the 

hardware and software interface of Libra systems running under level Epsilon compatible 

MCP. The information in this manual applies to Libra 680, 690, 750, 780, 790, 880, 890, 

4000, 4100, 4200, and 6200 systems, unless specified otherwise. 

Incorporated in this manual are descriptions of supported data types, the processor 

state, and operator set. In addition there are appendixes that list the alphabetical 

operator codes, the numeric operator codes, common actions, and interrupts. 

The primary audience for this manual is system analysts, whose responsibilities include 

the need to gather and analyze information in order to provide software support for Libra 

systems running under level Epsilon compatible MCP. 

Prerequisites 

Users of this manual are expected to have full knowledge of the capabilities, features, 

and operation of Libra systems running under level Epsilon compatible MCP. 

Documentation Updates 

This document contains all the information that was available at the time of publication. 

Changes identified after release of this document are included in problem list entry (PLE) 

18875373. To obtain a copy of the PLE, contact your Unisys representative or access the 

current PLE from the Unisys Product Support Web site: 

http://www.support.unisys.com/all/ple/18875373 

Note: If you are not logged into the Product Support site, you will be asked to do so. 

6878 7530–007 1–1

Introduction 

1–2 6878 7530–007

Section 2 

Process Model 

This section discusses concepts associated with the process model that is implemented 

by level Epsilon MCP systems. It introduces fundamental data types and the processor 

state required for functional specification of the operator set. 

Addressing Granularity: Words 

The unit of addressing in the ClearPath MCP systems is the word, a memory unit made 

up of 48 data bits, a 4-bit tag, and a 4-bit data extension. Operators exist that can deal 

with parts of words; however, memory is addressed and accessed in whole words. The 

term item is more general than word; an item contains one or two words. 

The tag determines, at least in part, the item type. Tags are four bits wide. 

The most common data type is the single-precision operand with a tag of zero. Such 

words are used for numbers (integer and floating point), Boolean values, characters, and 

arbitrary encodings. For some purposes, pairs of words are joined to form double 

precision operands with tags equal to two. Most other tag values are used for words 

with special functions that are recognized by the processor. Some of these data types 

are distinguished entirely by their tag, some by a combination of tag and other fields 

within the word, and some by a combination of tag and context. 

Segments and Descriptors 

An aggregate of memory words associated for addressing purposes is called a segment. 

Segments may contain either data or code. This document refers to two classes of 

segments: virtual and actual. (The term virtual, as applied to segments, is not to be 

confused with the ordinary use of the term virtual memory; an actual segment may or 

may not be present in main memory.) 

Virtual segments are the objects manipulated by user programs; they are defined and 

referenced by special words called Data Segment Descriptors (DSDs) and Code 

Segment Descriptors (CSDs). The term Virtual Segment Descriptor (VSD) refers to the 

union of DSD and CSD. VSDs occur within the addressing environments of user 

programs, where they can be accessed and manipulated in limited ways. 

6878 7530–007 2–1

Process Model 

Actual Segments and Actual Segment Descriptors (ASDs) 

An actual segment is a contiguous group of memory words. 

An actual segment is defined by a special object called an Actual Segment Descriptor 

(ASD). An ASD is a multi-word data structure that specifies the location, length, and 

other attributes of an actual segment. All the ASDs in the system are in an array called 

the ASD table; each entry has a unique index called its ASD_number. Once "touched," 

each VSD contains the ASD_number of the actual segment to which it refers. 

The ASD table is outside the addressing environment of user programs; such programs 

refer to ASDs indirectly, by evaluating VSDs and other items that contain ASD 

references, but they do not manipulate the ASD_number references or ASD entries 

directly. 

Virtual Segments and Virtual Segment Descriptors (DDs and 

CSDs) 

Virtual data segments may be unpaged (represented by one actual segment of arbitrary 

length) or paged (subdivided into noncontiguous fixed-length actual segments, with 

possibly a shorter last page). Code segments are always unpaged. To an unpaged virtual 

segment there corresponds exactly one actual segment; in this case the virtual-actual 

distinction is not significant for the segment, but remains so for the descriptors, VSD and 

ASD. There are four classes of VSDs: 

untouched A request-token for a segment (or sometimes for a reference or other 

object). This is the only form of VSD constructed by user programs. 

original The defining and owning token for a segment. Touched original VSDs 

are created only by the operating system. 

unindexed copy A reference to the segment. Copies are created by operators that fetch 

original DDs from memory. Copy CSDs do not occur in user programs. 

indexed copy A reference to a specific element of the segment. Indexed DDs are 

always copies; they are created by Index operators from unindexed 

(original or copy) DDs. No indexed CSD is defined. 

An untouched VSD could be called untouched original. It typically serves as a request for 

an original DD or CSD, but it is actually a general binding-request token and can occur 

wherever a DD or reference is expected. Any normal access to a token is intercepted so 

that the requested object can be created in place of the token. 

The other three classes of VSDs are touched; they contain fields to locate and 

characterize the data in the segment. The element_size field of a DD indicates whether 

the virtual data segment is to be treated as an array of single words, double word pairs, 

or 4- or 8-bit (hex or EBCDIC) characters. All touched VSDs contain an ASD_number. The 

adjectives original, copy, unindexed, and indexed, when applied to a DD, imply touched; 

indexed also implies copy. 

Generally, there is one original VSD for a segment. However, functional operator 

definition does not require precisely one original DD for each array. 

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Process Model 

Arrays of 4-bit characters are called hex because four bits can encode one hexadecimal 

(base 16) digit. Arrays of 8-bit characters are called EBCDIC for Extended Binary Coded 

Decimal Interchange Code; the character encodings commonly used on ClearPath MCP 

systems. Certain operators associate particular hex or EBCDIC encodings with decimal 

digits or with + or - signs, but most character operators accommodate arbitrary 4- or 8-bit 

data. 

Procedures: Activation Records 

A procedure is a portion of a program, associating a group of parameters and 

declarations with a body of code. (This notion of procedure is consistent with the 

PROCEDURE or BLOCK of ALGOL, the PROCEDURE or FUNCTION of Pascal, and the 

SUBROUTINE or FUNCTION of FORTRAN.) 

An activation record (AR) can be considered the instantiation of a procedure; it is a group 

of consecutive words that provide space for the data and control objects occurring in the 

procedure. Each word (or double word item) corresponds to one object declared in or 

passed as a parameter to the procedure. Simple objects such as INTEGERs, REALs, or 

BOOLEANs occur as operands within the record, while more complex structures, such 

as ARRAYs are defined by descriptors in the record. Other word types occur as 

references. The declarations within a procedure may include other procedures, which are 

generally represented in the AR by Program Control Words (PCWs) defining their entry 

points. 

A program has a static hierarchical structure, in which each procedure occupies a fixed 

position. Objects declared within a procedure are considered local to it; they are 

instantiated as items in its AR. When procedure P declares procedure Q, Q is said to be 

nested within P. Conversely, P is said to contain Q, and items declared in P are 

considered global to Q. This characteristic of block-structured languages is modeled in 

the ClearPath MCP; the activation record of P is considered the immediately global 

activation record to that of Q. Procedure Q could, in turn, declare another procedure, R, 

and so on. Then Q is immediately global to R and P is more distantly global to R. 

Each visible object can be named by specifying the nesting depth of the declaring 

procedure and the relative position of the item in that procedure's activation record. Such 

names are called address couples and are the sole form of address appearing in the code 

of ClearPath MCP programs. An address couple is written (lambda,delta), where 

lambda the lexicographic level (nesting depth, usually abbreviated lex level) 

delta the position of the word in the activation record (displacement from the base of 

the AR). 

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Process Model 

Processes: Stacks 

A process is an execution of a program; it associates the program code with the data 

space and processing record for that execution (and separate from all other executions). 

A new process involves the activation of a single procedure; in the course of its 

execution, that procedure can activate procedures, which can activate procedures, and 

so forth. Only the most recently activated procedure in the process executes code; 

when one procedure calls another, the caller is suspended until the called procedure 

exits. (Not all the procedures activated in a process are necessarily from the same 

program.) 

Unlike procedure activation, which is performed automatically by the Enter operator, 

process creation is performed by operating system software. A process is terminated 

(also by software) when the initial procedure exits or is aborted. 

A stack can be considered the instantiation of a process. The stack contains a historical 

record of all procedures that have been entered and not yet exited. It contains the 

activation records for those procedures. It also serves as an expression stack; most 

operators take their arguments from the top of the stack and leave their results there. 

For each procedure that has been entered in a process and not yet exited, there is one 

frame in the process stack. The stack frame includes the activation record followed by 

any items that have been pushed onto the expression stack and not yet consumed. 

The system can use many stacks, with a processor assigned to one stack at a time 

(multiprogramming). A system can have more than one processor; at any time, each 

processor is bound to a different stack (multiprocessing). 

A stack is a special case of actual segment. Stacks are referenced by stack_numbers, 

which are a subrange of the ASD_numbers. Stacks are identified as such in their defining 

ASDs. 

Programs: Code Segment Dictionaries 

Executable code is contained in segments defined by Code Segment Descriptors, which 

occur in special segments called Code Segment Dictionaries. A code segment dictionary 

is a special case of an activation record, global to the outer block AR. The code segment 

dictionary can be considered the instantiation of a program; its AR is global to an arbitrary 

number of processes executing the same program. In addition to a CSD for each code 

segment in the program, this AR contains the Program Control Word (PCW) defining the 

outer block entry point; it may also contain Data Descriptors defining read-only data 

segments. To execute a program, software creates a code segment dictionary 

associated with the program code file. 

2–4 6878 7530–007

Linkages and Addressing Environments 

Process Model 

Activation records are linked onto two lists—the historical chain and the environmental 

chain—which are at the base of each activation record. 

The historical chain is a chronologically ordered list that consists of History Links 

connecting each stack frame to that of its initiating procedure (immediately below it in 

the same stack). A processor register (F) holds a pointer to the head of this chain for the 

active stack. Each link of the historical chain is contained in the History Word (HISW). 

The environmental chain defines the current addressing environment of a process by 

linking the activation record of each procedure to that of its containing, or immediately 

global, procedure. Each link of the environmental chain is contained in the Environment 

Word (ENVW). 

A normal Environment Link has two elements, stack_number and displacement, 

specifying a stack and the word index within the stack segment to the base of an 

activation record. A pseudo Environment Link is also defined; it has two elements, 

ASD_number and displacement, specifying an arbitrary segment and a small index. 

An AR constructed automatically on a stack by procedure entry is linked into the 

environmental and historical chains. It contains a Return Control Word (RCW) that 

preserves state necessary to resume processing at the activation record designated by 

the History Link. Such an AR is called a normal activation record to distinguish it from a 

pseudo activation record, which is created in an arbitrary segment by primitive software. 

A pseudo AR is linked into the environmental chain, but never as the topmost entry. This 

AR is not linked into the historical chain and it has no RCW. A stack can contain an 

arbitrary number of normal ARs, but a pseudo AR typically encompasses all or most of 

an actual segment. 

The current addressing environment is the set of activation records addressed by the 

environmental chain whose head is the current topmost AR, the one for the procedure 

whose code stream is currently bound to the processor. The position of an AR in the 

environmental chain defines its lex level. The lex level of the topmost AR is defined to be 

LL; there are LL+1 ARs in the current environment. Lex level 0 defines the end of the 

chain and denotes the most global AR. The processor maintains the current value of LL 

in a register. 

A processor register (D[LL]) points to the base of the current topmost AR and, therefore, 

to the top of the environmental chain. There is another register pointing to the 

immediately global AR, and so forth to the end of the environmental chain. These 

registers are called display registers and are treated as a vector; the most global AR is 

referenced by D[0], the next by D[1], and so forth up to D[LL]. Display registers are used 

to evaluate address couples. The base of the activation record for level lambda is 

designated by D[lambda]. (In principle, address-couple evaluation can be performed by 

traversing the environmental chain when lambda is less than LL, but satisfactory 

performance requires the use of display registers.) The registers are maintained 

automatically by the processor, which traverses the new environmental chain at 

procedure entry/exit and process stack switch. 

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Process Model 

A History Link always points to an HISW in the same stack; the historical chain is a linear 

structure that maps the sequence of procedure entries within a process. An ENVW 

Environmental Link may point at an ENVW in the same or another stack; the set of 

environmental chains forms a tree structure that maps the static block structure of a 

program. The historical and environmental chains are often called dynamic and static, 

respectively. Early versions of the system architecture used the term lexical for the 

environmental chain; the term lexicographic occurs in the literature of block structured 

programming languages, referring to the static structure of the program; hence, the 

phrase lexicographic level. 

References 

References to objects occur in several forms: 

1. An address couple in the code stream is consumed directly by an operator (such as 

Value Call, which fetches an operand). Address-couple evaluation depends upon the 

current addressing environment (context), because its lambda component specifies 

only a position on the current environmental chain. 

2. A Stuffed Indirect Reference Word (SIRW) is a context- independent reference 

formed by transforming an address couple with a Name Call operator, which 

replaces the lambda component of the address couple by an environment link to the 

activation record at lex level lambda in the current addressing environment. 

An SIRW is created from an address couple to designate an item in the current 

environment, but once formed it continues to designate that item when passed into 

other environments. 

3. An unindexed copy DD is a reference to a segment. Such copies are formed from 

original DDs by Load operators. 

4. An indexed copy DD is a reference to an element of a segment; it may also be used 

to designate the first element of a sequence. Indexed DDs are formed from 

unindexed DD by Index operators. 

5. A Program Control Word (PCW) constitutes a specialized reference to a code stream. 

PCWs define procedure entry points; they also designate destinations for jumps 

between segments. A PCW is generated by special Make PCW operators. 

A PCW also contains other information about the code, including the lex level at 

which an entered procedure will run. 

6. An Absolute Store Reference Word (ASRW) is a special reference used by a few 

operators to access memory by absolute address. ASRWs are not manipulated in 

user programs; they are mentioned here because they appear in the definitions of 

some partly restricted operators. That is, the operators occur in user programs and 

the operators can consume an ASRW, but ASRWs do not occur in user programs. 

2–6 6878 7530–007

Protection 

Process Model 

The term protection refers to mechanisms and techniques that control the access of 

executing programs to stored information; protection is one aspect of the much larger 

topic of security. 

The protection mechanisms in ClearPath MCP processors can be described as a 

modified capability architecture. A capability is defined as an unforgeable ticket that 

grants the possessing subject (process or procedure) the right to access a designated 

object (data) in specified ways (such as read, write). (The term modified denotes that 

there are restrictions on the access to and manipulation of the capabilities themselves.) 

The remainder of this section is a brief overview of the protection mechanisms. 

The fundamental protection policy is that a procedure can access only the objects in its 

extended addressing environment. The access modes of primary interest are read, write, 

and enter; additional accesses include create, destroy, and exit. A procedure creates 

objects by pushing words onto the stack, including operands that define simple objects 

and untouched DDs that define more complex ones. Exiting a procedure destroys all the 

objects declared in it; the RCW serves as an exit capability (usable once only). The 

environmental chain provides, via address couples, read and write capability to objects in 

the addressing environment. An SIRW or a DD provides read and usually write capability 

to the referent. A PCW serves as an enter capability. 

Protection is a responsibility shared by the processor (hardware and firmware) and the 

software. The responsible software includes the user language compilers, which are 

constructed to follow a number of conventions in all generated code. In particular, the 

unforgeability property of capabilities is enforced by the compilers, which do not emit 

sequences of code that could create or modify a capability contrary to the policy. The 

compilers are also "trusted" to generate only valid address couples. 

Accessing Segments 

Enforcement of segment boundaries is a key element of the protection mechanism. 

Data in segments (other than from ARs) is accessed via IndexedDDs; enforcement is 

based on controlling the generation and use of IndexedDD: 

1. IndexedDDs are formed by index operators, which apply an index value to a DD. 

Both unindexed and indexed DDs can be indexed; reindexing an IndexedDD 

algebraically adds the new index to the current index. The index operations require 

resulting index values to be not less than zero, and to be less than the segment 

length specified in the referenced ASD. All index bound enforcement is at word 

boundaries. 

Indexing a paged DD proceeds in two steps: 

a. The index is divided by the page length. 

b. The quotient is used to index the page table and fetch the unindexed page DD, 

which is then indexed by the remainder from the division. 

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Process Model 

The upper bound on unpaged arrays is determined by the length of the segment; the 

upper bound on paged arrays is determined by the length of the page table, the fixed 

page length, and the length of the last page. Indexing a paged unindexed DD 

proceeds in two steps, as described previously; the quotient must be a valid index 

on the page table. Reindexing a paged indexed DD is more complicated, but the 

result is as though the sum of the current and new index values were applied to the 

unindexed DD. 

2. Load and store operators consume an IndexedDD to access the referenced word or 

double-word. Load and store operations require the word index in an IndexedDD to 

be less than the segment length specified in the referenced ASD. 

3. Array operators use an IndexedDD to access one or a sequence of elements of an 

array; they may modify the IndexedDD while traversing the array. Array operators are 

bounded by the length in the ASD. 

4. Certain operators make repeated read access to a membership or translate table, 

indexing an IndexedDD by a function of the character values in a sequence. Table 

access requires the word index in an IndexedDD to be less than the segment length 

specified in the referenced ASD. 

The boundaries of code segments and edit tables are enforced statically by the 

compilers. 

Access Control 

In their roles as capabilities, the descriptors, references, and other control structures 

offer access rights to the holder. Some of these rights can be controlled individually for 

each instance of the structure. 

An indexed or unindexed DD has a write-access right that can be disabled. Write access 

is required for any memory write (store) operation. A write-disabled DD is often called 

read only. The default state is write enabled. 

An IndexedDD has a reindex right that can be disabled. Reindex must be enabled for the 

IndexedDD to be used as an argument to an indexing, array, or set- element_size 

operator. The default state is reindex enabled. 

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Addressing 

Process Model 

The only addresses that appear in a code stream are static address couples 

(lambda,delta). The maximum valid values of lambda and delta are respectively LL and 

the offset of the last item declared in the referenced activation record. 

Simple variables, references, and other one- and two-word objects reside in an activation 

record and can be addressed directly by an address couple. When the addressed object 

is a reference (SIRW or copy DD), it can be evaluated to provide access to its referent. 

Larger memory objects, such as arrays and multi-word structures, typically reside in 

segments outside the stack and are defined by original DDs within the stack or within 

other segments. An element of an array declared in a procedure can be addressed by 

providing an integer index value and the address couple of the descriptor. If that element 

is an indexable descriptor, it can be indexed, and so forth. 

Code is addressed by PCWs. In general, the entry point of a procedure is specified by a 

reference to its PCW and the activation record in which the PCW occurs becomes the 

immediate global addressing space for the new AR instantiating the procedure. Also, the 

PCW itself (rather than the reference) can be used to enter a procedure whose 

immediate global AR is within the current addressing environment. 

The term addressing environment refers to the set of activation records that constitute 

the current procedure and its globals. The items in that environment are directly visible 

via address couples. Other items, arrays, elements, and code are indirectly visible 

because references or original DDs for them are visible. These indirectly visible objects 

may themselves contain referenced or original DDs that render other objects indirectly 

visible, and so on. The union of the directly and indirectly visible objects constitute the 

extended addressing environment of the procedure. 

Procedure Entry/Exit 

Normal activation records are created on the top of the stack by a sequence of 

operations that effect procedure entry: 

1. A Mark Stack operation defines the base location for the beginning activation record, 

creating a new HISW on top of the stack and linking it at the head of the historical 

chain. An “inactive” ENVW, identical to the new HISW, is placed above the HISW. 

At this step, a history, but not an environment, link exists and the incipient AR is 

actually within the expression stack of the initiating process. 

2. A reference to the code for the procedure is placed on the stack. 

3. Any parameters for the procedure are placed on the stack. 

4. An Enter operation is performed. The new AR is now linked into the environmental 

chain; the addressing environment and code stream for the new procedure are 

established. The reference to the new procedure is replaced by a special structure 

called a Return Control Word (RCW), which designates the invoking code and 

preserves other states necessary to resume the invoking procedure when the 

invoked procedure is completed (exits). 

6878 7530–007 2–9

Process Model 

5. The new AR may now be extended as the prologue (stack-building) code in the new 

procedure pushes objects onto the stack. Such objects may include operands to 

define simple scalar objects, untouched descriptors to define additional segments or 

binding requests, PCWs to define nested procedures, and so forth. At first, these 

objects are in the expression stack; an explicit Push operator must be executed to 

make the new objects accessible via address couples. An Enter operation implicitly 

causes a push to display the parameter words already on the stack, which occupy 

the low order part of the new AR. 

In explicit procedure invocation, a program performs each of the previous steps by 

executing appropriate operators. In addition to explicit procedure entry, there are two 

mechanisms in which entry is implicit; in these cases, the relevant Steps 1 through 4 

occur automatically: 

• An interrupt is an entry (into an operating system procedure) that is performed 

automatically by the processor because an operator is unable to perform its function 

or because some condition requires software action. 

• An accidental entry occurs when a PCW is encountered during the evaluation of a 

reference chain. The designated procedure is invoked as a function with no 

parameters; it is expected to return either another reference or the target of the 

reference chain. This mechanism is provided to support the call-by-name parameter 

semantics of ALGOL-60. The invocation of an accidental entry procedure is often 

called a thunk. 

The topmost stack frame is deleted from the stack by an Exit operation; the historical 

chain is used to locate the prior entered AR and reinstate its stack frame and addressing 

environment, and the RCW is used to resume the code stream. 

Expression Stack and Stack Frames 

The current expression stack occurs at the current top of the process stack, immediately 

above the topmost activation record. A processor register (S) maintains a pointer to the 

top of the current stack. (The topmost several words of the stack may themselves be in 

registers; the remainder of the stack is in main memory.) 

If a procedure is invoked when the current expression stack is not empty, the expression 

values remain in the stack below the new AR. Upon procedure exit, the topmost 

expression stack is discarded along with the topmost AR, and the previous stack is 

reinstated. 

The term stack frame is applied to the combination of the activation record and the 

expression stack of a procedure. The distinction is that address couples and SIRWs can 

designate only items in the activation record. The boundary between the expression 

stack and the topmost activation record is determined by the length of the activation 

record. A Push operation enlarges the activation record to include the expression stack. 

The distinction between activation record and expression stack is maintained by 

convention. The processor enforces no distinction, but the results of addressing a word 

in the expression stack are undefined. 

2–10 6878 7530–007

Stack and Display Registers 

Process Model 

The processor maintains several registers that designate the current stack, historical 

chain, and addressing environment. 

• SNR contains the stack_number of the stack to which the processor is currently 

bound. This value serves as a unique process identifier throughout the life of the 

process; it is available to user programs for that purpose. 

• S designates the top of the expression stack. 

• F designates the topmost HISW, the head of the historical chain. 

• D[lambda] designates the base of the activation record at lex level lambda in the 

current addressing environment. 

• D[LL] designates the topmost entered ENVW (at the base of the topmost activation 

record), the head of the environmental chain. 

Some, but not all, of these registers are accessible directly by programs. When accessed 

by programs, S, F, and D[LL] are defined to contain displacements relative to the base of 

the stack designated by SNR. The obsolete register BOSR is defined as a constant zero, 

so that differences such as S-BOSR generate the intended value. 

Executable Code Streams 

Variable-length operator sequences are stored in arrays of program code words called 

code segments. Each program code word contains six 8-bit containers called syllables. 

The term code stream pointer is used to describe a reference to the entry point of an 

operator sequence in a code segment. A code stream pointer consists of a reference to 

the code segment and indexes to a word and syllable within the segment. 

The code segment reference is the ASD_number of the segment. The processor retains 

this number in a register, Program Segment Number (PSN). 

The entry point in the code segment is indicated by the Program Word Index (PWI), 

which is relative to the base of the code segment, and the Program Syllable Index (PSI) 

within that word. The processor maintains PWI and PSI in registers. 

Processors retain additional information about the code stream: 

• The LL register holds the lex level of the current procedure. 

• The CS Boolean indicates whether the processor is in normal state or control 

state. In control state, the processor defers most asynchronous interruptions of the 

code stream until a normal state is resumed. User programs almost always run in a 

normal state. 

6878 7530–007 2–11

Process Model 

General Boolean Accumulators 

Processor state includes several Boolean accumulators that are used by several operator 

groups. Their use and definition are discussed in Section 4 and are summarized in 

Appendix B. 

TFFF: True/false flip-flop. 

OFFF: Overflow flip-flop. 

EXTF: External sign flip-flop. 

FLTF: Float flip-flop. 

A variety of operators interact with TFFF, OFFF, and EXTF; the values of these registers 

are automatically saved and restored by procedure entry and exit. FLTF is used only 

within sequences of special edit operators. Its value is preserved as necessary when 

these sequences are interrupted and resumed. 

CxxD and SxxD operators require an immediately following RTFF. TFFF will be undefined 

after these sequences (CxxD RTFF and SxxD RTFF). 

ASD Memory Architecture 

Each memory word is directly named by an absolute address, which is an integer in the 

range 0 to memory size–1. The memory size depends on the configuration of particular 

systems. The maximum memory size supported by each processor type is as follows: 

Processor Type Maximum Memory Size 

Libra 680/780/880 2**34 words (16 GW) 

Libra 4000 2**32 words (4 GW) 

Libra 4100/4200/6200 2**39 words (512 GW) 

System memory is subdivided into contiguous regions, called segments, which are 

defined by ASDs. Direct access to absolute addresses is limited to low-level system 

software; ordinary references to memory are accomplished indirectly, by citing a 

segment (ASD_number) and a segment-relative offset; the address is derived from the 

ASD for that segment. (Even references via address couples are ultimately defined by 

ASDs.) 

All the ASDs in the system are located in a structure called the ASD table. This table is at 

a fixed location, which starts at absolute address = 0. 

2–12 6878 7530–007

Section 3 

Data Structure and Text 

Most data types are defined in this section; others are defined later in the context of the 

operators involved. The definitions in this section apply to all Level Epsilon MCP 

systems. 

Word Format 

Words have 48 information bits plus 4-bit data extensions and four tag bits. The 

information bits are numbered from 47 to zero, from the high-order bit down to the loworder 

bit. Word formats are conventionally diagrammed with the bits shown in groups of 

four and the tag separated from the 48-bit body of the word. 

 

 

47 43 39 35 31 27 23 19 15 11 7 3 

 

 

 

46 42 38 34 30 26 22 18 14 10 6 2 

e t 

 

x a 

45 41 37 33 29 25 21 17 13 9 5 1 

t g 

 

 

44 40 36 32 28 24 20 16 12 8 4 0 

 

 

A field of a word is denoted [first:length], where 

first is the bit number of the high-order bit of the field (first less than or equal to 

47). 

length is the field length in bits (length less than or equal to 48). 

Fields are often given names, such as "offset" for "[12:13]." A field of an object or the 

class formed by applying the field specification to a class of objects is denoted by 

suffixing the field name or specification to the object or type name with an interposed 

dot, such as x.[46:1] or SIRW.offset. 

6878 7530–007 3–1


When necessary, fields are wrapped around from the lowest-order bit to the 

highest-order bit. If length is greater than first+1, then length minus (first+1) bits are 

concatenated starting from the highest-order bit (47). The following sequence illustrates 

the field [first:length] in the case where length is greater than first+1: 

47,46, ... , first , ... ,0,47,46, ... , last , ... ,1 

 

length 

Word types are distinguished by tag value and frequently by additional type bits in the 

word. Tag values are specified using hexadecimal notation. 

Throughout this document, word types are referred to by type name or acronym. 

Because the data type double precision consists of two words, the term item is used 

(instead of word) to refer to an entity whose type may be double precision. 

Data Words 

A Data Word is defined as a word that, when present in memory, can have its contents 

rewritten by a normal store (as opposed to overwrite) operation. (Words of all other 

types may be protected from normal stores.) Data Words serve primarily as computation 

arguments, rather than as reference arguments or control structures. 

Data Words include those with tags in {0, 2, 4, 6}. 

The term Data Word denotes a union of data types; these types are defined in the 

following paragraphs. Their definitions are the same for all ClearPath MCP systems. 

Operands (Single and Double Precision) 

The great majority of data items dealt with by programs are operands. There are two 

operand types: 

single precision a single word with a tag of 0 

double precision: a pair of words both with a tag of 2 

Throughout this document, the unqualified term operand is used solely to refer to the 

union single and double precision type. 

Neither operand type has a unique interpretation applied to it. Operators, according to 

their function, apply to different interpretations. For example, operands are interpreted as 

numeric values, bit vectors, and character sequences by arithmetic, word manipulation, 

and pointer operators, respectively. Numeric and Boolean operands are generated and 

interpreted by a wide variety of operators and are defined in this section. Section 3 

defines additional operand interpretations with the operator groups that apply them. 

3–2 6878 7530–007


The terms single and double precision convey the usual notion of alternate numerical 

representations with different precision and range, as defined in the following 

paragraphs. However, the same terms define data types regardless of the interpretation 

being applied. 

Real Numeric Operands 

Many operators interpret operands as numeric values. The structure of the numeric data 

is defined in this section; details of numeric interpretation are found in the operator 

descriptions under "Numeric Operand Interpretation" in Section 4. 

A single precision floating point operand is represented as a single precision operand 

with the following fields: 

[ext] Not used 

[47: 1] Not used 

mant_sign [46: 1] Mantissa sign (0=positive, 1=negative) 

exp_sign [45: 1] Exponent sign (0=positive, 1=negative) 

exponent [44: 6] The power of eight by which the mantissa is scaled 

mantissa [38:39] The integer magnitude of the number before scaling 

The mantissa field can be regarded equivalently as 39 binary or 13 octal digits; the latter 

view is suitable because floating point numbers are scaled by powers of eight. 

A single precision floating point operand with an exponent equal to zero is used as the 

canonical representation of a single precision integer; an operand in this form is called 

single_integer. The largest single_integer magnitude is 2**39-1 = 8*13-1. 

The form "k-bit integer" (where k is an integer in {1 to 39}) is used to specify an operator 

output value in which field [47:48-k] contains zero. The same term is used to specify an 

operator input value in which fields [46:1] and [44:45-k] contain zero or field [44:45] 

contains zero. (Bits 47 and 45 are insignificant in integer representations; bit 46 is 

insignificant if the value is zero.) 

A double precision floating point operand is represented as a double precision operand 

with the following fields: 

First word: 


[47: 1] Not used 



exponent [44: 6] The low order 6 bits of the exponent 

mantissa [38:39] The integral portion of the mantissa 

6878 7530–007 3–3


Second word: 


hi_order_exp [47: 9] The high order 9 bits of the exponent 

mantissa [38:39] The fractional portion of the mantissa 

A double precision floating point operand with an exponent equal to 13 is used as a 

canonical representation of a double precision integer; an operand in this form is called a 

double_integer. (A double precision operand with exponent and mantissa zero is also a 

valid double_integer.) The largest double_integer magnitude is 2**78-1 = 8*26-1. 

Decimal Sequence Operands 

Some operators generate or consume operands interpreted as a sequence of decimal 

digits. Each digit is represented as a 4-bit binary integer in the range {0 to 9}. (Hex 

sequence representations of decimal data are often called Binary Coded Decimal, BCD.) 

A digit sequence is an unsigned sequence of decimal digits. Digit sequences generated 

by binary-to-decimal conversion operators contain only true digits; however, digit 

sequences that are inputs to pointer operators may include nondigits, which are hex 

characters in the range {hex "A" to hex "F"}. Up to 12 or 24 digits can be contained in a 

single or double precision operand, respectively; the second word of a double holds the 

low order digits. Depending on the operator, the digit sequence is left- or right-justified 

within the operand. The extension is not used. 

Boolean Operands 

Some operators generate and other operators consume operands interpreted as Boolean 

values. The Boolean values true and false are represented as binary 1 and 0, 

respectively. The terms True and False are used to specify Boolean values. In the 

specification of a stack output from an operator, True and False are defined as the 1-bit 

integer values 1 and 0, respectively. In the specification of a stack argument for an 

operator, True and False are defined as operands with bit [0:1] equal to 1 or 0, 

respectively; Boolean interpretation ignores field [47:47] of any operand, the extension, 

and the second word of a double precision operand. 

Boolean operands are generated by the relational operators, among others. Operands are 

interpreted as Boolean values by the branch operators and Assert operators. The logical 

operators do not interpret Boolean values; rather, they perform Boolean arithmetic on 

the argument bit vectors. 

3–4 6878 7530–007

Tag-4 Word and Tag-6 Word 


Tag-4 and tag-6 words are data words, but the only interpretation applied to them is as 

48-bit vectors by a class of computational operators. A zero word with a tag of 6 is 

conventionally used as an uninitialized single datum. 

These words cannot normally be fetched to the expression stack as operands and they 

are not valid arguments for arithmetic computational operators. However, they may be 

fetched with the LOAD operator and may be stored over by normal store operators. 

Program Code Words 

Variable length operator sequences are stored in arrays of program code words called 

code segments. Each program code word contains six 8- bit containers called syllables, 

numbered 0 to 5 from high order to low order. (The mapping of each operator into 

syllables is specified in Section 4.) 

s[i] = [47-(8*i): 8] Syllable i, for i = 0 to 5 

Program code words have tags of 3, except for special sequences called Edit Tables, 

which have tags of 0. The extension is not used. 

Actual Segment Descriptors (ASD) 

An ASD is an eight-word structure; the first three constituent words are called ASD1, 

ASD2, and ASD3. 

The ASD table is a two-dimensional array containing eight words per ASD: ASDi[j] is 

defined for j (ASD_number) in {0 to 2**27-1} and i in {1 to 8}. The table is stored in 

memory as a linearized array beginning at absolute address zero: 

ASDi[j] = Memory[4*j + i-1] 

ASD[0] is the first ASD entry in the table. It can be accessed with the RASD and WASD 

operators, but 0 is not a valid ASD_number for a reference. Processors are not required 

to detect the use of 0 as an ASD reference, so software should never create a valid 

ASD[0]. 

ASD1 contains the absolute memory address of the first word of the actual segment (if 

the segment is present in memory) and several other bits of information concerning the 

status of the segment. 

ASD2 defines the length of the actual segment. 

ASD3 may contain a reference to the Virtual Segment Descriptor that defines the virtual 

segment corresponding to this actual segment. For a paged virtual segment, the ASD3 

for each page must be a reference to the page descriptor in the page table. 

The other ASD words have no defined function in the processor; they are reserved for 

software use. 

6878 7530–007 3–5


Actual Segment Descriptor, First Word (ASD1) 

Memory management of the actual segment uses two presence indicators and an 

address field. ASD1.present_to_proc must be 1 for any access to the contents of the 

segment by a data processor or any access by an I/O processor, except I/O data transfer. 

ASD1.present_for_IO must be 1 for any use of the segment as the source or destination 

for I/O data transfer. If ASD1.present_to_proc or ASD1.present_for_IO is 1, ASD.address 

is the absolute address of the first word of the segment; otherwise, the address field 

contains a software-encoded value. 

ASD1 (Tag = 8) 


segment_type [47: 2] Segment’s memory type (see “Platform Memory”) 

present_to_proc [45: 1] Segment-is-present indicator for non-I/O access 

(0=absent, 1=present) 

Alias-protection [44: 1] Blocks cache based on ASD 

hlt [43: 1] Enables switch-dependent halt when executing code 

from this segment 

not_stack [42: 1] Stack indicator (0=stack, 1=not stack) 

present_for_IO [41: 1] Segment-is-present indicator for use as an I/O buffer 


access_modify [40:1] Must be zero 

address [35:36] If present_to_proc and present_for_IO are both zero, the 

address field is interpreted by software; otherwise, it 

contains the base address of the actual segment 

Actual Segment Descriptor, Second Word (ASD2) 

An ASD2 specifies the length of the segment; the remainder of the word is reserved for 

software use. AS_length specifies the actual-segment length for all operations that 

access data in the segment. The deficit and nybbles fields are used (in addition to 

AS_length) by the GLEN operator to report the user-declared length of the segment. 

ASD2 (Tag = 8) 


[47: 8] Reserved for coexistence 

nybbles [39: 4] 4-bit frames in addition to net words 

deficit [35:16] Words less than AS_length-derived length 

AS_length [19:20] Actual-segment length in words 

3–6 6878 7530–007

Absolute Store Reference Word (ASRW) 


An ASRW references an individual item in memory via an absolute address. ASRWs are 

recognized by a restricted set of operators: LODT, OVRD, OVRN, RDLK, and TWOD. 

ASRW (Tag = B) 



address [38:39] Absolute address 

Virtual Segment Descriptor (VSD) 

Virtual Segment Descriptor (VSD) refers to the union of word types that describe virtual 

segments. A VSD is called a DD or CSD when used to define a data segment or a 

program code segment, respectively, but there is not always a distinction in the form or 

structure of the descriptors. 

The following paragraphs describe the attributes of VSDs that are necessary for 

functional definition of the operators; not all of these attributes are subject to direct 

manipulation in user programs. Code in user programs manipulate only those fields that 

have uniform structure and interpretation across all ClearPath MCP systems. 

Untouched DD 

An untouched DD is encoded as a word with a tag equal to five and field [47:2] equal to 

zero. (All tag 5 words are untouched DDs.) 

By convention, the fields within [45:46] of an untouched DD correspond to those in a 

touched original, except that the ASD-reference field contains a software encoded value 

and the element_size is seven when the requested object is not an ordinary data 

segment (array). However, the contents of an untouched VSD are determined more by 

software convention than by operator functional definition. 

Unindexed (Original and Copy) DD 

Unindexed (original or copy) DD (Tag = C or E for unpaged or paged, respectively) 

ASD_ref ext [ext] ASD_number ms 4 bits (see below) 

copy [44: 1] Copy bit (0=original, 1=copy) 

read_only [43: 1] Read-only bit (0=read/write, 1=read-only) 

element_size [42: 3] DD: array element type (0=single precision, 

1=double precision, 2=hex, 4=EBCDIC; 3,5,6,7 are invalid) 

CSD: Reserved for software 

[39:20] Reserved for software 

ASD_ref [19:23] ASD_number ls 23 bits 

6878 7530–007 3–7


Note: For an unindexed paged DD, the ASD_number is that of the page table. 

(Unindexed DDs for the pages occur in the page table, but the user program has no 

direct access to them.) 

A touched CSD is identical to a read-only unpaged original DD, but the element_size is 

not significant to the processor. By convention, touched CSDs are originals; however, 

this rule is not enforced by the processor. 

The terms word descriptor and WordDD are used for descriptors whose element_size 

values are single or double (precision); the terms character descriptor and CharDD are 

used for descriptors whose element_size values are EBCDIC or hex. The terms 

SingleDD and DoubleDD are used for WordDDs with element_size single and double, 

respectively. 

The no_write (read_only) bit in a DD can be set to prevent use of the DD for write access 

to the data. 

The following fields are defined for use in user code files. User programs may set, but 

should never reset, the read_only bit. 

read_only [43: 1] 

element_size [42: 3] 

IndexedDD (Indexed Data Descriptor 

Indexed copy DDs are called IndexedDDs. ) 

IndexedDD (Tag = D or F for unpaged or paged) 


reindex [44: 1] Controls indexing, Data Array, and set-element_size operators 

(0=disabled, 1=enabled) 

read_only [43: 1] Read-only bit (0=read/write, 1=read-only) 

element_size [42: 3] The type of array element (0=single precision, 1=double 

precision, 2=hex, 4=EBCDIC, and {3, 5, 6, 7} are invalid values) 

index [39:20] Used if element_size is single or double precision: the word 

index from the base of the array to the referenced item 

char_index [39: 4] Used if element_size is EBCDIC or hex: the index within the 

word of the referenced character 

word_index [35:16] Used if element_size is EBCDIC or hex: the index from the base 

of the array to the word containing the referenced character 


3–8 6878 7530–007


The following fields are common to indexed and unindexed DDs and function identically: 

read_only, element_size, and ASD_ref. 

The reindex bit indicates whether the IndexedDD grants access to just the array element 

it references or to the entire segment. If reindex is disabled in an IndexedDD, the 

indexing operators cannot reindex it, the array operators cannot use it, and operators 

cannot change the element_size. 

An indexed word descriptor is called an IndexedWordDD or, more specifically, an 

IndexedSingleDD or IndexedDoubleDD. An indexed character descriptor is called an 

IndexedCharDD. These terms are sometimes abbreviated IWDD, I1DD, I2DD, and ICDD. 

The interpretation of the index to the referenced element depends on element_size. For 

IndexedWordDDs, the index field is the word index from the base of the array or page to 

the single precision word or to the first word of the double precision word pair. For 

IndexedCharDDs, the index field consists of two subfields: word_index, the index from 

the base of the array or page to the word containing the referenced character, and 

char_index, the character index within the word. Char_index must not exceed 5 and 11 

for EBCDIC and hex IndexedCharDDs, respectively. Char_index 0 designates the 

highest-order character in the word. 

The following fields are defined for use in user code files. User programs may set, but 

should never reset, the read_only bit. 

read_only [43: 1] 

element_size [42: 3] 

char_index [39: 4] Used if element_size is EBCDIC or hex 

Code Segment Descriptor (CSD) 

CSDs occur in untouched and touched original forms, which are analogous to untouched 

and original DDs. 

An untouched CSD is a word that occurs in a code segment dictionary with a tag of 3 

and field [47:2] equal to zero. This encoding is not necessarily unique, but other words so 

encoded must not appear in a code segment dictionary where they may be the target of 

the (sdi,sdll) address couple in a PCW skeleton. 

Touched CSDs are unpaged original DDs (defined previously) with write access disabled; 

the element_size field is reserved for software. Code and data segments are not 

interchangeable, however, because data-fetching operators cannot access code words 

and processors cannot execute data words. 

6878 7530–007 3–9


Virtual Segments 

An unpaged virtual segment is a single actual segment; it cannot exceed 2**20-1 words 

in length. An IndexedCharDD can designate only the first 2**16 words of an unpaged 

segment. 

A paged virtual segment is represented by several actual segments: a page table and 

one or more pages. The page table contains an untouched or original DD for each page. 

Any unindexed DD for the segment has a special tag designated "paged" and refers to 

the page table. Any indexed DD for the segment designates an element of a particular 

page. The page DDs (the original DDs in the page table) are not marked paged, but the 

IndexedDDs designating elements in pages have a special tag. 

All pages are 2**13 words long, except the last page in a virtual segment, which must 

be shorter. If a paged virtual segment has a length equal to an integer multiple of 2**13, 

the processor requires that the page table have an additional last page with length equal 

to zero. 

The ASD for each page contains a reference to the original DD for that page; this 

reference is an IndexedSingleDD whose ASD_ref designates the page table and whose 

index is the page index. This back link from page to page table is essential for automatic 

page switching operations. 

In summary, a paged virtual segment is a two-layer structure; the DD for the whole 

segment specifies the page table, which contains a DD for each page. An unused page 

has an untouched DD; for each touched page, the DD refers to the defining ASD. 

MaxLen defines the maximum length of a paged virtual segment. This integer value 

varies by each processor type as follows: 

Processor Type Maximum Paged Virtual Segment 

Length 

Libra 680/780/880 (2**13) * (2**20 - 1) - 1 

Libra 4000 (2**27) - 1 

Libra 4100 (2**32) - 1 

Libra 4200/6200 (2**13) * (2**20 - 1) - 1 

MaxInx defines the largest integer value allowed for character indexing and iteration 

counts associated with pointer operations. MaxInx is defined as MaxLen * 12. 

3–10 6878 7530–007

Virtual Index 


Any word or character in a virtual segment can be specified by an integer called its virtual 

index. The virtual index of the element is the zero-relative ordinal of that element when 

the entire segment is considered as an array of elements of that size. An equivalent 

operational definition of virtual index is as an integer that can generate an IndexedDD 

designating the element when the integer is applied by the Index operator to an 

unindexed DD that designates the virtual segment and has the appropriate element_size. 

This definition of virtual index can be extended to double precision elements only for 

elements with even word alignment within the segment. Because double precision 

elements can occur with odd alignment, it is more useful to define the virtual index of a 

double item as the virtual index of its first word. 

The virtual index of an IndexedDD is stored in as many as three components: 

1. The page index (pX), for a paged segment, designates the page; it is an index into 

the page table. The pX value is implicit, because the IndexedDD is a copy of 

page[pX] of the page table. The ASD referenced by the IndexedDD contains a 

reference to the page descriptor; the reference is an IndexedSingleDD with pX in its 

index field. For an unpaged segment, pX is defined to be zero. 

2. The word index (wX) designates the referenced word within the actual segment; 

wX is in the index field of an IndexedWordDD or in the word_index field of an 

IndexedCharDD. 

3. The character index (cX) designates the referenced character within the word; 

cX is in the char_index field of an IndexedCharDD. 

The virtual index (vX) for an IndexedDD is computed from these three values, according 

to the element_size of the IndexedDD: 

single or double: vX = pX*2**13 + wX 

4 bit: vX = (pX*2**13 + wX)*12 + cX 

8 bit: vX = (pX*2**13 + wX)*6 + cX 

6878 7530–007 3–11


References 

Of the various reference types, unindexed and indexed DDs are virtual segment 

descriptors and are defined previously. This section defines address couples, SIRWs, 

PCW literals, and PCWs. 

Address Couples 

Fixed Fence Address Couples 

Address couples in several operators are encoded in 16 bits with a 4-bit lambda value in 

field [15:4] and a 12-bit delta value in field [11:12]. 

Extended Address Couples 

Address couples in NMCn and VLCn operators have an implicit lambda equal to n (limited 

to 0, 1, 2, or 3), and a 16-bit delta value in the parameter. 

Variable Fence Address Couples 

Address couples in NAMC and VALC operators are encoded in 14 bits with a variable 

fence between lambda and delta. Taking advantage of the fact that lambda must be less 

than or equal to LL, the number of high-order bits interpreted as the lambda value varies 

with the value of LL at evaluation time. The remaining low-order bits are interpreted as 

the delta value. The following table gives explicit ranges: 

LL range bits left of fence lambda range delta range 

{0 to 3} 2 {0 to LL} {0 to 2**12-1} 

{4 to 7} 3 {0 to LL} {0 to 2**11- 1} 

{8 to 15} 4 {0 to LL} {0 to 2**10-1} 

The lambda value is the reverse of the bits to the left of the fence; the delta value is 

taken from the bits to the right of the fence. Following are examples of address couple 

interpretation. Each pair is the same address couple representation, but notice the effect 

of the dynamic fence indicated by the colon (:). 

1. a. at LL= 2, 10:000000010011 => (1,19) 

b. at LL=13, 1000:0000010011 => (1,19) 

2. a. at LL= 5, 101:00001000000 => (5,64) 

b. at LL= 3, 10:100001000000 => (1,2112) 

CSD Address Couples 

Address couples of Code Segment Descriptors occur in PCW skeletons. These use a 

fixed fence form with lambda in [13:1] (called sdll) and delta in [12:13] (sdi). 

3–12 6878 7530–007

Environment Links 


An Environment Link specifies an activation record by identifying the segment that 

contains it and the number of words from the base of the segment to the ENVW at the 

AR base. User programs do not manipulate Environment Links, but they are fundamental 

to an understanding of addressing. 

An Environment Link is a meta-field that is defined here as an object with several 

components, so that the entire Link can then be considered a single field in the words in 

which it occurs (SIRWs and entered ENVWs). An Environment Link has two possible 

formats: 

normal Environment Link 

stack_num ext [ext] The stack_number ms 4 bits (see below) 

pseudolink [47: 1] 0: denotes normal env_link 

stack_num [46:15] The stack_number (ls 15 bits) identifying the 

stack containing the referenced location 

stack_disp [31:16] The displacement from the base of the stack to 

the ENVW of the normal activation record 

pseudo Environment Link 

seg_num ext [ext] ASD_number ms 4 bits (see below) 

pseudolink [47: 1] 1: denotes pseudo env_link 

seg_num [46:23] 

[23:2] 

The ASD_number (ls 23 bits) identifying the 

segment containing the referenced location 

reserved 

seg_disp [21:6] The displacement from the base of the segment 

to the ENVW of the pseudo activation record 

Normal activation records are constructed automatically by procedure entry. Pseudo 

activation records are constructed only by privileged software, which also must forge 

pseudo links in SIRW references to PCWs placed within the record. Procedure entry via 

those references to those PCWs causes the pseudo AR to be linked into the 

environmental chain as the immediate global AR of the entered procedure; within the 

procedure (and any procedures local to it), SIRWs constructed to address couples within 

the pseudo AR will automatically have pseudo links. 

6878 7530–007 3–13


Stuffed Indirect Reference Word (SIRW) 

An SIRW is created by the NAMC, LNMC, and NMCn operators from an address couple 

to provide a context-independent reference to the same location. 

SIRW (Tag = 1) 

env_link 

[ext] 

[47:32] 

Designates activation record in which reference occurs 

offset [15:16] The offset from the base of the AR to the referenced location 

SIRW.offset corresponds to address couple delta. 

Together the env_link and offset fields address an item in an activation record. The item 

is located in the segment designated in env_link, indexed by the sum of the 

displacement in env_link plus the offset. Some operations, notably procedure entry, 

require both the displacement and offset, from which ordinary referencing uses the sum. 

Program Control Word (PCW) 

PCW (Tag = 7) 


[44: 3] Zero 

pwi [41:13] The PWI code stream pointer component 

psi [28: 3] The PSI code stream pointer component 

control_state [25: 1] CS Boolean (0=normal state, 1=control state) 

[24: 1] Must be zero 

lex_level [23: 4] The lex level at which the activation record runs 


The PCW code stream pointer consists of the field pwi, psi, and ASD_ref. The lex_level 

field specifies the lex level of the activation record associated with the designated code. 

The control_state attribute specifies execution in normal and control state. 

3–14 6878 7530–007


User programs do not manipulate PCWs. However, they do provide the skeletons from 

which PCWs are constructed by the MPCW operator. The following is the structure of 

the PCW skeleton. 

[47:12] Zero 

skeleton_psi [35: 3] The PSI code stream pointer component 

skeleton_pwi [32:13] The PWI code stream pointer component 

skeleton_CS [19: 1] The initial value of the CS Boolean (0=normal state, 1=control 

state) 

[18: 1] Zero 

skeleton_LL [17: 4] The lex level for the procedure 

sdll [13: 1] The lambda component of an address couple designating CSD 

sdi [12:13] The delta component of an address couple designating CSD 

Stack Structure and Linkage 

The contents of a process stack include a top-of-stack control word at the base of the 

stack, followed by an arbitrary number of words used by software and then an arbitrary 

number of stack frames. 

There are three data types used for stack frame linkage: a History Word (HISW), an 

Environment Word (ENVW), and a Return Control Word (RCW) appear at the base of 

each stack frame for linkage. 

A Top of Stack Control Word (TSCW) is used to preserve processor state in an inactive 

stack (a stack to which no processor is bound). 

These structures are not unambiguously typed; their recognition depends in part upon 

the context in which they are accessed. 

With certain exceptions involving the RCW, user programs do not manipulate stack 

linkage words. Their attributes are defined in the following subsections for purposes of 

defining the operator function, and for completeness. 

6878 7530–007 3–15


Stack Frame Linkage 

There are three words (HISW, ENVW, and RCW) at the base of an entered normal 

activation record. The ENVW is at offset 0 and the RCW at offset 1. No HISW or RCW is 

used with a pseudo AR. 

The HISW is built by the Mark Stack operation: 

HISW (Tag=1) 

stack_num ext [ext] Stack_number ms 4 bits (see below) 

[47: 1] Zero 

stack_num [46:15] Stack number (ls 15 bits) containing the HISW 

history_disp [31:16] Displacement of prior HISW 

history_opt [15:1] 1:historical chain search not required 

Pop/action [14:7] Codes showing pop optimization data or action 

requirements 

disable_ext [7:1] 1:disable maskable externals when exit 

float_status [6:2] variant rs resumption status 

rs [4:1] restart indicator 

extf [3:1] EXTF (external sign) 

offf [2:1] OFFF (overflow) 

tfff [1:1] TFFF (true/false) 

block_exit [0:1] 1:Exit generates interrupt 

The block_exit bit indicates whether or not a service interrupt is to be generated when 

the activation record is deallocated. The enter operators always initialize this bit to 0 

(disarmed). It can be set to 1 by software, in which case it must be reset to 0 by 

software before an Exit operation can deallocate this AR. 

The entered ENVW and RCW are built by the Enter operation; they occur only in entered 

ARs: 

3–16 6878 7530–007

Entered ENVW (Tag = 3) 

env_link 

RCW (Tag = 7) 

[ext] 

[47:32] 

[15:16] Undefined 


Designates activation record in which reference occurs 


[44:3] Zero 


psi [28:3] The PSI code stream pointer component 

control_state [25:1] CS Boolean (0=normal state, 1=control state) 

exit_opt [24:1] 0: no optimization information 

1: exit only updates D[new LL], except if new 

LL is greater than old LL, also updates down to 

D[old LL] 

lex_level [23:4] The lex level at which the activation record runs 


The stack linkage retains state necessary to reestablish and resume the procedure that 

invoked the current procedure. The RCW preserves for exit the same components 

provided by the PCW for procedure entry, specifying the code stream pointer, lex level, 

control state, and privileges. The rs indicator indicates whether the first operator in the 

resumed code stream should execute in restart or initial mode. The general Boolean 

accumulators are also preserved. 

Top-of-Stack Linkage 

When a processor is bound to a stack, its processor number is stored as an integer in 

the base word of the stack. The stack is said to be active; the processor is said to be 

"running in" the stack. When the stack is inactive (has no processor bound to it), the base 

word contains a TSCW, which points to the topmost activation record in the stack. 

TSCW (Tag = 3) 

stack_num ext [ext] The stack_number ms 4 bits (see below) 

[47:1] Must be zero 

stack_num [46:15] The stack_number (ls 15 bits) identifying the stack 

containing the referenced location 

stack_disp [31:16] Displacement to topmost HISW 

offset [15:16] Offset of top of stack from topmost HISW 

For MVST, the topmost activation record of the stack being activated simply replaces the 

topmost activation record of the deactivated stack, for the same code stream that 

executed the MVST. 

6878 7530–007 3–17


For start-up (see “Startup Request”), the inactive stack has an extra activation record on 

an inactive stack, consisting of an HISW, an inactive ENVW, and an RCW. The 

HISW.history_link designates the topmost HISW on the stack when it was (and will 

become) active; the RCW defines the code stream associated with the active process. 

The TSCW designates this extra AR; its displacement points to the HISW and its offset 

is 2, designating the RCW. 

Protected Object Word (POW) 

Three forms of Protected Object Words (POWs) are defined: 

• A soft POWis reserved for software use. 

• A restart POW can be used as an extra argument for operators in restart mode. 

• A hard POW is recognized by the processor for containing TCU event tokens. 

In each case, the purpose of the data type is to provide unique representations of 

information that is protected from access by the normal fetch and store operators. 

Soft POW (Tag = A, [46: 1] = 0) 

[46: 1] 0: denotes software POW 

[45:47] 

[ext] 

Reserved for software 

Reserved for software 

Restart POW (Tag = A, [47: 4] = 5) 

[47: 4] Binary 0101: denotes restart POW 

[43:44] 

[ext] 

Reserved for hardware 

Reserved for hardware 

Hard POW (Tag = A, [47: 2] = 3) 

[47: 2] Binary 11: denotes hard POW 

[45: 2] Reserved for software 

[43: 4] Binary 0011: denotes event 

[39: 7] Reserved for software 

[32: 1] If 1, the IOP will not cause event 

[31:32] TCU event token 

[ext] Reserved for software 

3–18 6878 7530–007

Tag Values 


Throughout this document, tag values are specified in hexadecimal notation. 

In most operations, the application and recognition of tags is automatic. Only the 

Read-Tag and Set-Tag operators (RTAG and STAG) elicit evaluation or assignment of tag 

values in programs; these are used very sparingly in user programs. 

The following tag levels uniquely determine the data type. User programs can use STAG 

to construct words of these types, although many other operators generate, manipulate, 

and transform operands. 

Tag Type 

0 single precision operand 

2 double precision operand 

4 tag-4 word: non-operand bit vector 

6 tag-6 word: non-operand bit vector, 

uninitialized single datum 

The following tag values characterize, but do not necessarily uniquely determine, the 

type: 

Tag Type 

1 SIRW 

3 untouched CSD 

5 untouched DD 

7 PCW 

9 NIRW (Libra 4000/4100/4200/6200 systems) 

D,F IndexedDD 

User programs construct SIRWs, PCWs, and IndexedDDs using appropriate referencegeneration 

operators. They occasionally modify such words, but not their tag values. 

They construct untouched DDs using STAG. Compilers place images of untouched CSDs 

into user program code files; they are not constructed with STAG. 

User programs occasionally use RTAG to determine the types of words that are 

parameters to procedures; the following assumptions are valid: 

• Operands, tag-4, and tag-6 words have unique even tags 

• SIRWs have tag 1 

• IndexedDDs have odd tags other than 1 

6878 7530–007 3–19


For example, if the type of a formal parameter to a procedure is a discriminated union of 

{single operand, SIRW, IndexedDD}, the tag of the parameter word can be used to 

discriminate the actual parameter type. Within the specified union, an even tag denotes 

an operand and an odd tag denotes a reference with 1 marking an SIRW and any other 

valid odd value an IndexedDD. 

Data Structure Access 

All the data structures defined in this manual are involved automatically in the action of 

some operator. Data items can also be constructed or manipulated by software using 

relatively primitive operators, such as fetch, bit-field operations, and store. For most data 

types, primitive access is restricted to MCP code at a low level of abstraction; only a few 

types are subject to primitive access by code in user programs. The following paragraphs 

outline the primitive operations that user programs can apply to data of various types. 

This text is by no means a rigorous specification of such code. 

Only operands are subject to unrestricted manipulation. The use of tag-4 and tag-6 words 

is governed by convention between the compilers and the MCP. 

Construction of descriptors is limited to untouched DDs in which field [47:2] contains 

zero and [45:46] contains an encoding according to compiler/MCP convention. 

Manipulation of DDs is restricted to copy descriptors, which are fetched with the LOAD 

and indexing operators. Copy DDs may be stored, provided that a copy must not 

continue to exist after the segment to which it refers is gone. Copy descriptors can be 

stored by ordinary programs only into normal activation records, where they may readily 

be found if necessary. Modification of copy descriptors by primitive means is permitted; 

however, it is restricted to altering the element_size field, altering the char_index field, 

and setting the read_only bit. 

On Libra 4000/4100/4200/6200 systems, Name Call operators construct NIRWs. On 

other Libra systems, Name Call operators construct SIRWs. SIRWs may be fetched with 

LOAD; they may be stored by user program code, provided that a stored reference does 

not outlive the referent. Modification of SIRWs by primitive means is permitted and is 

restricted to (under special circumstances) altering the offset field. 

Operators are provided to modify element size in copy DDs and the access rights in copy 

DDs. These operators should be used in preference to primitive operations. 

PCWs are built on the stack by Make PCW operators. They can be fetched only with 

Load Transparent and can be stored only into the appropriate activation record. 

Primitive code in user programs should not access any other data structures. Stack 

linkage words and code segment descriptors need not be accessed directly. ASDs and 

ASRWs do not occur within the addressing environment of user programs. 

3–20 6878 7530–007

Section 4 

Interrupts 

This section generally applies to all ClearPath MCP systems, but many details are 

specific to just the Epsilon systems. 

Interrupt Mechanism 

Superhalt 

An interrupt is an automatic invocation of a procedure; the mechanism is defined as the 

common action aINTE. (A related mechanism, called accidental entry, is defined in 

Section 5 of this manual as common action aACCE.) Exit from the interrupt procedure, 

when practical, resumes execution of the interrupted code stream. 

Operator-dependent interrupts (ODIs) are invoked directly by the current operator to 

request an MCP service required by the operator or to report a programming or operator 

fault. Spontaneous interrupts (SIs) generally cannot be associated with a particular 

operator; some involve execution of the code stream and some do not. 

When an operator may report several interrupts, there is generally no requirement that 

one interrupt take precedence other than that imposed by the function of the operator. 

When processing actions are functionally sequential, interrupts generated by an earlier 

action take precedence; otherwise, interrupts generated by any part of the operator may 

be reported. (For example, if some item B is meaningful only when item A is interpreted 

in a particular way, an error in that interpretation of A must take precedence over an error 

detected in B.) If a conditional action of the operator is not performed, interrupts that 

might have been generated by it are not required. (For example, if the interpretation of A 

is such that B is not significant, then any errors that might have been detected in B need 

not be reported.) 

A superhalt condition occurs when the processor cannot process an interrupt condition. 

In such cases, the processor halts in a state from which normal continuation is not 

possible. The following conditions cause a processor to superhalt: 

• When an interrupt loop is detected and the Interrupt_Count register reaches the 

maximum value. 

Upon interrupt entry, the register increments by one and can only be reset by the 

restricted operator ZIC (Zero Interrupt_Count). 

• When a fatal initialization error occurs. 

• When the restricted operator MVST (Move Stack) encounters an interrupt condition 

such that a processor cannot recover to a valid stack environment. 

6878 7530–007 4–1

Interrupts 

• When a processor moves to a stack that has an invalid ASD1 or ASD2 entry. 

• When a processor moves to a stack that has an invalid or inconsistent TSCW 

For example, S is less than F. 

• When a fatal error occurs while a message is queued up or removed from an 

operational module (Libra 4000 only). 

Interrupt References 

An interrupt reports the occurrence of some set of circumstances called the interrupt 

condition. Each distinct interrupt condition generates a different interrupt reference, 

which can invoke a unique procedure for that condition. An interrupt reference is an 

SIRW designating a fixed location within either (1) a dedicated stack called the interrupt 

vector or (2) adjoining locations in the D[0] activation record. The referent is called the 

interrupt slot. The unqualified word "interrupt" is often used to refer to the interrupt slot, 

the reference, or the interrupt condition that generates that reference. The interrupt 

reference is the head of the reference chain for an interrupt procedure; the interrupt slot 

can contain another SIRW or the PCW for the procedure. 

Most interrupt conditions that use the interrupt vector are assigned a single slot; these 

are called Condition-Vectored Interrupts (CVIs). Several conditions are assigned a 

separate slot for each operator that can generate the interrupt; these are called Operator- 

Vectored Interrupts (OVIs). The interrupt vector contains two activation records: one for 

CVIs and one for OVIs. Not all the slots are assigned in either AR. 

The interrupt conditions that use the D[0] activation record are called Maskable External 

Interrupts (MEIs). Their interrupt slots must contain the PCW for the procedure. 

Vector Interrupt Formats 

Two interrupt formats, or calling sequences, are used by the interrupt vector cases: 

Programmed Operator Interrupt (POI) and Restartable Operator Interrupt (ROI). Each 

format is named for a particular application to which it is particularly suited, although 

neither is restricted to a single application. 

POI 

POI is an interrupt format that facilitates operator emulation. The arguments to the 

operator are provided as parameters to the interrupt procedure, so they are readily 

accessed by the procedure and are automatically discarded by procedure exit. 

Operator emulation can be required because a defined operator is not implemented or 

because normal domain or range of operation is exceeded (such as, arithmetic 

underflow). In emulation cases the interrupt procedure is expected to return any required 

results of the operation; the code stream resumes with the next operator. 

Some spontaneous interrupts use the degenerate form of POI format with no parameter. 

4–2 6878 7530–007

ROI 

Interrupts 

ROI is an interrupt format suited to reporting service exceptions so that the operator can 

be repeated, for example in restart mode. Input arguments to the interrupted operator 

are pushed onto the stack below the interrupt AR; the interrupt procedure is provided 

two parameters: P1 and P2. The parameters are both single words. P1 sometimes 

contains diagnostic data; if not defined, it is zero. P2 typically designates to software the 

object that is erroneous or in need of service. 

Code Stream Designation and Resumption 

The interrupt entry generates an RCW that designates the resumption point in the code 

stream. 

Often, the RCW designates the operator whose execution generated the interrupt. The 

VARI syllable is designated in the interrupt RCW for a variant operator. Similarly, the 

enter-edit operator is designated when an edit operator is interrupted; for table edit, an 

updated table pointer designates the edit operator. (An initial table pointer is an 

IndexedDD; in the restart mode of TEED or TEEU, the updated table pointer is an 

IndexedDD.) 

Resumption of the code stream is a key concern in interrupt definition; important 

resumption issues include: 

1. If the code stream can be resumed 

2. If so, the action required by the interrupt procedure 

3. The operator that is designated by the interrupt RCW 

4. If that operator is to be executed in initial or restart mode 

If the code stream can be resumed from the interrupt procedure, the required exit 

operator is specified; otherwise, the code stream is said to be defunct and must be 

aborted. The following is an explanation of this notation: 

Abort Resumption is impossible and undefined. (It may be possible to resume the 

program at some other point in the code after appropriate adjustment of the 

process stack.) 

EXIT The interrupt procedure must exit, not return. 

RETN The interrupt procedure must return the appropriate result value for the 

emulated operator. 

RTN2 The interrupt procedure must return two appropriate result values for the 

emulated operator. 

REXI The interrupt procedure must fetch the P1 parameter to the top of the stack 

and execute the REXI operator. 

For resumable ODIs, the RCW may designate the operator that generated the interrupt, 

the next operator in the code stream, or the successor operator (not necessarily in 

sequence); these resumptions are called Repeat, Next, and Continue, respectively. 

Resumable SIs are considered to occur between operators in the code stream; the RCW 

designates the next operator to be executed and the resumption is called Continue. 

6878 7530–007 4–3

Interrupts 

Although "resumption" is a misnomer for defunct code streams, the term is used with 

the following notation: 

Abort-Lost: The RCW is undefined 

Abort-Here: The RCW designates the interrupted operator 

Abort-Next: The RCW designates the next operator 

Interrupt Parameters 

For ODIs in POI format, the interrupt parameters are the arguments to the interrupted 

operator. Each argument occupies two words on the stack; if the argument type is not 

double-precision, the second word is zero. 

For interrupts in ROI format, the second parameter, P2, varies according to the specific 

interrupt type; it is often used to designate the object of concern or other information 

about the circumstances of the interrupt. P2 is specified for each interrupt case that uses 

the ROI format. 

For several interrupts, P2 is specified to be a "proper reference" (either an SIRW or an 

IndexedDD) to the object of concern. The P2 parameter is a copy of the reference the 

processor was evaluating when an exception was detected; if that reference is an 

address couple (in an operator parameter or PCW skeleton), it is stuffed to yield an 

SIRW. 

The value of P2 or of any POI parameter may be used in several ways: 

• It is used by operating system software in performing some service invoked by the 

interrupt. Such use can occur for interrupts that have parameter values specified and 

have resumptions other than Abort. (Such interrupts are flagged "S" or "s".) 

• It is used by operating system or diagnostic software in analyzing software and 

hardware failures for reporting, logging, or recovery. This use is characteristic of 

alarm interrupts. It sometimes occurs with enforcement interrupts; for example, 

some software distinguishes an uninitialized datum from other unacceptable items in 

an Invalid Target. 

• It is available (typically in diagnostic dumps) for users who are troubleshooting a 

failure, although it is not analyzed programmatically. This use characterizes all 

interrupts that can report significant parameter values and are not instances of the 

first two cases. 

• In addition, for Invalid Code Word, Invalid Target, and Missing PCW, P1 is the 

offending target, except that tag = 2 is changed to tag = 0. 

Interrupt parameters are never unrelated to the circumstances of the interrupt. P2 is 

never an original DD or a POW. 

4–4 6878 7530–007

Restart Configuration 

Libra 6xx and 7xx systems use restart mode in two types of situations: 

Interrupts 

• Accidental entry in Value Call and almost all interrupts in Value Call: the extra state is 

the current reference. 

• Most interrupts during all data array operators, except for short-source and unpack 

operators (which are repeated from the beginning when interrupted at a page 

boundary): the extra state defines the processing already accomplished and is in a 

restart POW. Note that an unpack operator may create restart mode, but does not 

use it. 

The extra state is left immediately below the interrupt AR and rs is set; the operator in 

restart mode consumes the extra argument. 

Also, when rs is true, certain operators have additional extra arguments in order to 

simplify their implementation: 

• SRCH has a length equal to one greater than the result of GINX on the domain 

argument. 

• EXPU has a dummy source argument. 

• Pointer scan operators have a dummy destination argument. 

• Vector operators with 4 or 5 arguments have dummy arguments to match the scalar, 

stride_A, stride_B, length, vector_A, and vector_B pattern. 

Operator Subdivision 

Libra 6xx and 7xx systems are unable to complete the longest feasible Data Array 

operations within a single Loop Timer interval. Therefore, it provides for the long Data 

Array operators to be divisible. If some stimulus (such as an MEI) is pending, the 

operator is interrupted, the stimulus serviced, and the operator resumed. Data Array 

operator subdivisions are the only instances in which some stimulus service occurs 

within an operator. Masked stimuli remain pending if the processor is in control state; 

control-state software must avoid excessively long array operations. 

The word Data Array operators (vector, word transfer, and search operators) are divisible 

between iterations. 

The character Data Array operators (not including short source, unpack, and skip 

operators) are divisible upon completion of each destination word (source1 for character 

sequence operators and source for scan operators). 

6878 7530–007 4–5

Interrupts 

Interrupt Definition 

Interrupts are defined in seven categories, which are presented in this section under 

separate headings for convenience rather than as correspondence to any grouping of 

interrupts slots or formats. The following are the types of interrupt definitions: 

• Arithmetic 

• Service 

• Enforcement 

• Alarm 

• Asynchronous 

• External 

• Maskable External 

Within this document, information on interrupt conditions is presented in specific 

notation as described here. 

Key information about each interrupt condition is summarized in a line containing six 

items in three groups, as follows: 

OVI:SUBT POI(x,y) Next RETN(big(x-y)) ODI E 

CVI ROI Repeat REXI(P1) ODI S 

CVI POI( ) Continue EXIT SI Se 

The condition group (CVI or OVI) and format (ROI or POI) are specified at the left. For 

OVIs, which are vectored by opcode, the operators are identified. For POIs, the 

parameters are indicated, often as dummy identifiers that are clear from the operator 

definition; an ellipsis indicates generically that the arguments to the interrupted operator 

are provided. Empty parentheses indicate the degenerate POI format in which there are 

no interrupt parameters. 

The resumption situation is specified in the middle of the line, using the notation defined 

previously. Return values are indicated for resumptions involving return. The notation is 

local to each interrupt definition and often involves the POI parameters. 

At the right end, the interrupt is informally classified as operator dependent or 

spontaneous (ODI or SI) and as service or error. 

Interrupts are categorized as service requests or error reports, with the following 

notation: 

S: Service 

Se: Service, sometimes treated as error 

SE: Service by definition although likely to be Error 

E: Error 

Es: Error although capable of being interpreted as Service 

ES: Error by definition although often used as Service 

4–6 6878 7530–007

Arithmetic Interrupts 

Interrupts 

Section 5 of this manual defines the arithmetic operations and includes five exception 

conditions: 

• Divide by Zero 

• Exponent Overflow 

• Exponent Underflow 

• Precision Loss 

• Integer Overflow 

In the vectored interrupt mechanism, each exception generates one of only three 

generic interrupts, each an OVI. In some cases the interrupt procedure must examine 

the operator arguments in order to establish which exception to report, if any. When the 

code stream is to be resumed, the interrupt procedure must return the appropriate 

operator result. 

The processor is permitted to generate an arithmetic interrupt in certain situations for 

which the operation, as defined in Section 5, is not exceptional. These interrupts are 

called spurious. The interrupt procedure must emulate the operator and produce a proper 

result. 

A spurious arithmetic interrupt is deemed a service interrupt; the interrupt procedure 

emulates the operator and resumes the code stream without reporting any exception to 

the rest of the software. Otherwise, an arithmetic interrupt is deemed an error report. 

The interrupt procedure determines the nature of the exception, if necessary, and takes 

appropriate software action for that exception. If the code stream is to be resumed, the 

procedure supplies the appropriate exception result for the operator. 

Throughout this section, the word type refers to single- or double-precision operands. 

Each arithmetic interrupt procedure must implement the type rules defined in Section 5 

for the interrupted operator. 

Arithmetic Overflow 

Arithmetic Overflow interrupts are generated by arithmetic operators when the result 

exponent is too large to represent and by the divide operators when the divisor is zero. 

This interrupt reports the Exponent Overflow and Divide by Zero exceptions. 

OVI:ADD POI(x,y) Next RETN(big(x+y)) ODI E 

OVI:SUBT POI(x,y) Next RETN(big(x-y)) ODI E 

OVI:MULT POI(x,y) Next RETN(big(x*y)) ODI E 

OVI:MULX POI(x,y) Next RETN(bigdp(x*y)) ODI E 

OVI:DIVD POI(x,y) Next RETN(zero(x,y) or big(x/y)) ODI E 

OVI:IDIV POI(x,y) Next RETN(zero(x,y)) ODI E 

OVI:RDIV POI(x,y) Next RETN(zero(x,y)) ODI E 

OVI:SNGL POI(x) Next RETN(bigsp(x)) ODI E 

OVI:SNGT POI(x) Next RETN(bigsp(x)) ODI E 

6878 7530–007 4–7

Interrupts 

The interrupt procedures for the divide operators report Divide by Zero when the second 

parameter (y) is zero. The code stream can be resumed by returning zero of the 

appropriate type, as follows: 

zero(x,y) z AND y AND 0 

In all other cases of Arithmetic Overflow interrupt, the interrupt procedures report 

Exponent Underflow. For operators that produce real values, the code stream can be 

resumed by returning the largest representable magnitude of the appropriate type and 

sign: 

big(x+y), big(x-y) biggest value with type x OR y and sign of x 

big(x*y), big(x/y) biggest value with type x OR y and sign of x*y 

bigdp(x*y) biggest dp value with sign of x*y 

bigsp(x) biggest sp value with sign of x 

The "biggest value" is a single- or double-precision operand with all bits in the exponent 

and mantissa fields set to one and the exponent sign set to zero. 

Arithmetic Underflow 

Arithmetic Underflow interrupts are generated by arithmetic operators when the result 

exponent is too small to represent. This interrupt reports the Exponent Underflow and 

Precision Loss exceptions. It may also report spurious conditions for several operators. 

The interrupt is generated when the final result of a computation has an exponent value 

that is negative and too large in magnitude to be contained in the exponent field. 

OVI:MULT POI(x,y) Next RETN(R(x*y) or zero(x,y)) ODI ES 

OVI:MULX POI(x,y) Next RETN(RD(x*y)) or zerodp) ODI ES 

OVI:DIVD POI(x,y) Next RETN(R(x/y) or zero(x,y)) ODI ES 

OVI:RDIV POI(x,y) Next RETN(x MOD y) ODI S 

OVI:SNGL POI(x) Next RETN(zerosp) ODI E 

OVI:SNGT POI(x) Next RETN(zerosp) ODI E 

OVI:NORM POI(x) Next RETN(zero(x)) ODI E 

For RDIV, the interrupt is always spurious; the procedure must emulate the operation 

and return a representation, in the proper type, of the defined result. 

The interrupt procedures for the other dyadic operators must emulate the operation and 

determine which of the following three actions to take: 

1. If the result magnitude is less than half the smallest representable value, the 

procedure must report Exponent Underflow. The code stream can be resumed by 

returning zero of the proper type, such as: 

zero(x,y) x AND y AND 0 

zerodp dp zero 

4–8 6878 7530–007

Interrupts 

2. If the result can be represented in nonzero unnormalized form, but is too small to 

normalize, and has nonzero low-order bits that must be discarded because of the 

inability to normalize (R* < > R), the procedure must report Precision Loss. The code 

stream can be resumed by returning the nearest representation (in proper type). 

3. If neither of the two previous situations holds true, the interrupt is spurious; the 

result can be represented in nonzero unnormalized form without loss of precision 

(R* = R). The procedure must resume the code stream by returning a 

representation, in the proper type, of the defined result; no exception is reported to 

the rest of the software. 

For NORM, SNGL, and SNGT, normalization is required and therefore, the interrupt is 

never spurious. The interrupt procedures must report Exponent Underflow. The code 

stream can be resumed by returning a zero of the proper type: 

zero(x) zero of same type as x, for example x AND 0 

zerosp sp zero 

Integer Overflow 

An Integer Overflow interrupt is generated for the Integer Overflow exception. 

OVI:NTGR,NTIA POI(x) Next RETN(maxsp(x)) ODI E 

OVI:NTGD,NTTD POI(x) Next RETN(maxdp(x)) ODI E 

OVI:IDIV POI(x,y) Next RETN(max(x/y)) ODI E 

OVI:RDIV POI(x,y) Next RETN(zero(x,y)) ODI E 

OVI:BCD POI(x) Next RETN(nines(param)) ODI E 

OVI:DBCD POI(x,n) Next RETN(nines(n)) ODI E 

All interrupt procedures for these interrupts report Integer Overflow. The code stream 

may be resumed by returning the appropriate values that are defined as follows: 

max(x/y) biggest integer with type x OR y and sign of x*y 

maxdp(x) biggest dp integer, (8**26)-1, with sign of x 

maxsp(x) biggest sp integer, (8**13)-1, with sign of x 

nines 4"999999999999" 

nines(n) IF n

Interrupts 

Service Interrupts 

The interrupts defined in this section usually constitute requests for an MCP service that 

is an extension of the hardware operators. In some situations, especially limiting cases, 

no service can be provided and the interrupt must be treated as an error. 

Absent Segment 

An Absent Segment interrupt is generated by operators requiring access to a segment 

that is not present in memory. The interrupt is generated when access is attempted via a 

touched DD or a PCW or RCW or environment_link whose ASD_ref field designates an 

ASD with ASD1.present_to_proc equal to zero. 

Two Absent Segment conditions are defined, one for code and one for data. Absent edit 

tables are reported as absent data. 

Absent Code Segment 

CVI ROI Continue EXIT ODI S 

The interrupt is generated when access is attempted via a PCW or RCW whose ASD_ref 

field designates an ASD with ASD1.present_to_proc = zero. P2 is identical to the 

interrupt RCW, which references the absent segment. 

The interrupt RCW contains the code stream pointer whose attempted distribution 

encountered the absent segment; after the code segment has been made present and 

the ASD has been changed, an exit from the interrupt procedure will complete the enter, 

exit, or dynamic branch into the intended code segment. Note that HISW.rs is set in the 

interrupt RCW if an exit to restart mode was interrupted; this is an example of the 

preservation of restart mode. 

Absent Data Segment 

CVI ROI Repeat REXI(P1) ODI Se 

P2 must be an indexed DD or an SIRW that referenced the absent segment for those 

cases requiring service. When ENVW evaluation detects an absent segment, P2 is an 

equivalent SIRW. When edit table entry detects an absent segment, P2 is an IndexedDD 

designating the edit table; the interrupt RCW designates the TEED or TEEU operator. 

The service requested by an Absent Segment interrupt is for the software to make the 

absent segment present, after which the code stream can be resumed. It is the 

responsibility of software to ensure that all required segments are present for progress 

to be made. For example, various pointer operators require some or all of source, 

destination, and table (edit, translation, or membership) segments. Another example is 

that a short-source or unpack operator requires both pages be present if the operation 

crosses a page boundary, since Libra 6xx and 7xx systems repeat such operators from 

the beginning. Any required data segments and the code segment must be resident 

simultaneously for the operator to execute to completion. 

4–10 6878 7530–007

Block Exit 

CVI ROI Repeat EXIT ODI S 

Interrupts 

Exit operators generate a Block Exit interrupt when an attempt is made to deallocate an 

activation record that has HISW.block_exit equal to one. P2 is zero. 

Missing PCW 

CVI ROI Repeat EXIT ODI SE 

A missing PCW interrupt is generated by the Enter operation when the reference chain 

does not yield a PCW. P2 is an SIRW to the word that is not a valid SIRW or PCW. If the 

word at F+2 is not an SIRW or PCW, the Missing PCW interrupt is generated and P2 is 

an SIRW designating that word; in this case, SIRW.stack_disp designates the HISW at F. 

If the offending word is a binding request token (such as, untouched DD), the operating 

system can perform the service of replacing that token by an appropriate reference. In 

other circumstances, the interrupt is reporting an error associated with the entry 

reference chain. 

For the Libra 680 and 690 systems, P1 is the offending target, except that if its tag=2, it 

is changed to tag=0. 

Stack Overflow 

CVI POI( ) Continue EXIT SI Se 

Stack Overflow indicates that a push onto the expression stack has caused the size of 

the stack to exceed its limit. The interrupt is a request to the MCP to extend the stack 

segment. The interrupt is classed as Spontaneous because it is generated when the 

object is pushed into memory, not necessarily when it is placed into registers at the 

virtual top of stack. As an SI, Stack Overflow is said to occur between operators. The 

stack and code stream pointer are left in a configuration consistent with resuming the 

code stream with an enlarged stack segment. 

Stack Overflow interrupt is disabled by its generation or by the successful initiation of a 

Move-Stack operation; it is enabled by execution of SPRR for "register" 36 or by 

successful completion of a Move-Stack operation. The interrupt is not masked by the CS 

Boolean. 

While Stack Overflow is disabled, bounds checking on the current stack is disabled. 

Touch 

A Touch interrupt is used by operators to involve the MCP in the allocation or linkage of 

resources represented by untouched descriptors. The MCP service requested is to 

replace the untouched VSD with the appropriate item, which is typically an original VSD 

or a reference. 

6878 7530–007 4–11

Interrupts 

The P2 parameter is a proper reference to the untouched VSD. 

Three Touch conditions are defined: Touch Reference, Touch Load, and Touch CSD. 

Touch Reference 


A Touch Reference interrupt is generated when an untouched DD is encountered as a 

reference target by any operator (except ENTR and EVAL) that evaluates reference 

chains. (ENTR generates Missing PCW interrupt; EVAL treats the untouched DD as a 

valid target.) 

Touch Load 


The Touch Load interrupt is generated when an untouched DD is encountered in a fetch 

attempt by LOAD or the final load step of NXLN. 

Touch CSD 

CVI ROI Repeat EXIT ODI S 

The Touch CSD interrupt is generated when an untouched Code Segment Descriptor is 

encountered by one of the make PCW operators. 

If the initial reference is the PCW skeleton; P2 is an SIRW generated by considering the 

sdll and sdi fields as the lambda and delta components of the unstuffed address couple. 

The Touch Reference interrupt can occur at a page boundary in a data array operator, as 

a descriptor is reindexed for the next iteration. In addition to the P2 parameter 

designating the untouched DD, the operator must preserve a consistent set of 

arguments below the interrupt AR. Depending on the situation, the following techniques 

are used: 

1. The pointer skips, though defined as array operators, are effectively indexing 

operators. 

2. The short-source and unpack operators are repeated from the beginning. 

3. Restart mode is invoked in all other cases, causing the descriptors to be reindexed at 

the beginning of the next iteration. 

Unimplemented Operator 

OVI:... POI(...) Next EXIT/RETN/RTN2 ODI S 

The Unimplemented Operator interrupt is generated whenever a primary or variant 

operator is encountered for which an operator is defined in this document, but not 

implemented (at least in part) in the processor. 

4–12 6878 7530–007

The following actions are required to use operator emulation: 

• The appropriate number of stack arguments must be present as interrupt 

parameters. 

Interrupts 

• The interrupt RCW must be generated to point at the first syllable past the operator 

(including any code parameters). 

• An interrupt procedure must have been provided in OVI slot 3 for the operator; the 

procedure can be tailored for that one operator. The procedure receives the operator 

arguments as parameters in POI format. Any required code parameters must be 

fetched by the procedure from the code segment. The procedure must emulate the 

operation and then exit, returning the specified operator results, if any. 

Vector Arithmetic Exception 

OVI POI(POW) Repeat RETN(POW) ODI S 

OVI POI(scalar, POW) Repeat RTN2(scalar, POW) ODI S 

This interrupt is reported by vector operators when an arithmetic fault occurs during the 

execution of the operator. It is also used to report spurious interrupt conditions that 

occur in the equivalent scalar operators. 

Vector operators that do not include a scalar stack item pass one parameter to the 

interrupt procedure in POI format. This parameter has a POW tag and contains the 

iteration count for the operator in bits 31:32. Vector operators that do include a scalar 

stack item pass two parameters in POI format. The first is the scalar argument (single or 

double precision) and the second is the POW. Non-scalar cases and SUM and SUMA set 

bit 40 in the POW to indicate that RS state consists only of the normal arguments plus 

the POW, and excludes the extra “dummy” arguments included by users of RS state for 

these operators. 

If the interrupted code stream is to be resumed, system software needs to obtain the 

data items, perform the appropriate arithmetic operations on them, update the result 

location, increment the iteration count by one, and return the scalar (if any) and iteration 

count arguments. The resumption condition is Repeat- Return2 or Repeat-Return, 

depending on the presence or absence of a scalar stack item. 

The arithmetic exception causes the appropriate arithmetic operator to generate an 

arithmetic OVI. That procedure decides whether to report an error and whether to return 

an emulation result to the vector arithmetic interrupt procedure. 

Note: Libra 4000 and 4100 systems do not support Vector Arithmetic Exception 

interrupts. 

6878 7530–007 4–13

Interrupts 

Enforcement Interrupts 

The interrupts in this group are generated primarily to enforce the preconditions and 

invariants defined for proper operator function. (In some cases, the MCP may take 

corrective measures or otherwise remove the error situation and resume the code 

stream, in which case the interrupt was effectively a request for service. Such action is 

possible only with non-Abort resumption situations.) 

There are some differences among Level Delta and Epsilon systems regarding the 

extent of enforcement; details regarding interrupt format vary widely. Level Epsilon 

processors respond as described in the following paragraphs. 

Bounds Error 

A Bounds Error is generated for any of the following reasons: 

• The index argument to an indexing or OCRX operator cannot be integerized. P2 is 

zero. 

• The index argument to an OCRX operator is less than one or exceeds the ICW_limit 

value in the index control word. P2 is zero. 

• An attempt is made to index an unindexed DD or reindex or update an IndexedDD so 

that the new virtual index is less than zero or exceeds the length of the virtual 

segment. P2 is the out-of-bounds IndexedDD, with an unsigned index. 

• The word index of a DD exceeds field capacity: 2**20-1 for a WordDD, 2**16-1 for a 

CharDD, or 2**13-1 for an edit table designator. P2 is that IndexedDD with a 

truncated index, unless the element index magnitude exceeds 2**32- 1, in which 

case P2 is zero. 

• An attempt is made to access, or use INDX to reference, an item via an IndexedDD 

whose word index is greater than or equal to the word length of the actual segment 

designated by its ASD_ref. For an IndexedDoubleDD evaluated by NXLV, LOAD, 

STOx, or Value Call, both referent words must be in-bounds. P2 is the out-of-bounds 

IndexedDD. 

Accesses to source and destination sequences in pointer operators are subject to 

this check, except for the cases defined to generate Destination and Source 

Boundary interrupts. 

• The offset into an actual segment exceeds ASD2.AS_length-1, for: 

− Accesses via SIRWs, entered ENVWs, or TSCWs: P2 is the reference in SIRW 

format. 

− Accesses to code (first detected by bad “code word” tag), whether sequential, 

as static or dynamic branch destinations, or via procedure entry/return: P2 is an 

unpaged IndexedDD that references the out-of-bounds code word. 

− Accesses relative to register values (such as F, D[LL]). However, pushing a word 

onto the current stack beyond its end constitutes a Stack Overflow condition; 

the store must be performed and Bounds Error interrupt cannot be generated. 

P2 is an SIRW to the current stack whose stack_disp field equals the register 

value. 

4–14 6878 7530–007

Interrupts 

When Stack Overflow checking is disabled, no Bounds Error interrupt is generated for 

any access to the stack segment. Software must not use a DD to access the stack 

beyond its defined AS_length. 

Resumption is defined for the indexing and OCRX operators. 

For all cases of indexing operators and OCRX: 

CVI ROI Repeat EXIT ODI Es 

In all other cases, the code stream need not be resumable: 

CVI ROI Abort-Here ODI E 

Destination Boundary 

CVI ROI Repeat REXI(P1) ODI ES 

A Destination Boundary interrupt is generated by pointer operators (other than TWOD) 

that attempt to transfer data to the first element beyond the end of the destination 

virtual segment. 

P2 is the destination descriptor updated to the last+1 element of the segment. 

This interrupt ordinarily reports an error; however, there are two possible services that 

software can perform: 

• It can lengthen the destination segment. 

• It can terminate the operation, discarding the rest of the intended transfer. 

Software may extend the destination segment in one of several ways: 

• An unpaged segment can be extended by providing a larger actual segment 

associated with the same ASD. 

• A paged segment with a short last page can be extended by providing a larger actual 

segment associated with the same last-page ASD. 

• A paged segment with a long last page can be extended by providing a larger page 

table associated with the same ASD. 

• An unpaged segment can be converted to a paged segment. The ASD associated 

with the original segment can be used either as the new page table or as a page; an 

additional ASD is needed for the other. 

In the first three cases, the code stream can be resumed without any modification of the 

stack arguments. The fourth situation requires that all touched DDs referencing the 

destination segment (including the destination argument on the stack below the interrupt 

AR) be modified to designate the new segment; the tags must be changed and the 

ASD_ref and index fields may require change. 

6878 7530–007 4–15

Interrupts 

Unconditional transfer operators (TUND and TUNU, TRNS, TWSD and TWSU) may be 

terminated by setting the length argument (on the stack below the interrupt AR) to zero 

prior to resuming the code stream. The resumed operator will terminate. These 

operators always place their arguments on the stack in their original relative positions; 

the length is the topmost operand below the interrupt AR. Note that there is a restart 

POW above the arguments. 

False Assertion 

OVI:ASRT,AVER POI(b) Next EXIT ODI ES 

The False Assertion interrupt is generated by the ASRT and AVER operators when the 

stack argument is False. 

The interrupt is an error indication on the part of the program invoking ASRT or AVER, 

but it is also a service request for message generation or other software- defined error 

handling. The Boolean argument is passed as the interrupt procedure parameter. The 

code parameter to the ASRT operator can be fetched from the code segment; the 

interrupt RCW points at the syllable following the parameter. 

Invalid Access 


An Invalid Access interrupt is generated when an operator attempts to write to memory 

via a DD with write access disabled. If the DD is a stack argument, P2 is zero; otherwise, 

P2 is the SIRW that referenced the DD. 

Pointer operators that "require a destination" may generate the interrupt when the 

destination argument is read-only, whether or not a write is attempted. 

Invalid Argument or Parameter 


This interrupt is a notice that a stack argument or code parameter for an operator does 

not meet the type and value-range constraints that are preconditions for the operator. 

Most of the preconditions cited in the operator definitions in this manual are enforced by 

checks that generate this interrupt when not satisfied. The bulk of the checks are on 

stack arguments, so the interrupt is often referred to as Invalid Argument. P2 is the 

offending argument if it is a bad type (tag=2 changed to tag=0); P2 is zero for all other 

cases. 

Invalid argument or parameter tests fall into the following categories: 

• Type checks: Data types are defined by tags and, in some cases, additional 

discriminator bits within the word. Some data types are defined partly by context, so 

a tag check provides a partial verification. An Uninitialized Argument interrupt is 

generated instead of Invalid Argument whenever the offending argument has a tag 

of 6 or 4. 

4–16 6878 7530–007

Interrupts 

• Reindex checks:Indexing, Data Array, and set-element_size operators require 

indexed-descriptor arguments to have reindex enabled; the reindex-enable bit may 

be considered part of the data-type definition for acceptable arguments. 

• Argument value checks: An integer operand or a field in a word of some other 

type may be constrained to a particular range or subset of values. 

• Code parameter value checks: A code parameter may be constrained to a 

particular range or subset of values. 

• Consistency checks: some operators place type or value restrictions on one 

argument, depending on some characteristic or another. Examples include 

element_size matching in pointer operators and type consistency between store 

objects and targets. 

• Integer magnitude checks: Non-Integer Argument exception arises when any 

operator except NTGR invokes the RaI (algebraic round to integer) function and the 

result is TooBig. If the argument to be integerized is used as an Index, the exception 

is reported as a Bounds Error; otherwise, it is reported as an Invalid Argument. (Note 

that often an argument range is limited to a subset of the integers; in such cases, 

the more limiting check is specified. The TooBig result from the RaI function is 

regarded as greater than any represent able value, even when the argument of RaI is 

negative.) 

Invalid Code Word 

An Invalid Code Word interrupt indicates that a word accessed from the current code 

segment is not a Program Code Word. It is generated in table edit mode if the tag of the 

word is not zero and in all other modes of the tag is not three. 

The interrupt is classified as an SI because it is not associated with an identifiable 

operator. However, it is not at all independent of the code stream. 

• Primary or Variant: 

CVI ROI Abort-Here SI E 

If the processor is parsing code other than in edit mode, the interrupt RCW designates 

the first syllable of the operator that contains a syllable in the invalid word. If a VARI 

prefix has been encountered, that syllable is designated. (If a branch, enter, or exit 

destination begins in the bad word, the RCW designates that destination.) 

• Edit: 


When the processor is parsing code in edit mode, the interrupt RCW designates the 

enter-edit operator; the arguments to that operator are below the interrupt AR. For table 

edit, an updated table pointer designates the first syllable of the operator that contains a 

syllable in the invalid word. 

For all cases, P2 is an unpaged IndexedDD that references the offending code word, and 

P1 is the offending target word, except that if that word had tag=2, it is changed to 

tag=0. 

6878 7530–007 4–17

Interrupts 

Invalid Operator 

CVI POI( ) Repeat EXIT ODI Es 

An Invalid Operator interrupt is unconditionally generated by execution of NVLD (Invalid 

Operator). No other operator generates this interrupt. 

Invalid Target 

CVI ROI Repeat REXI(P1) ODI Es 

An Invalid Target interrupt indicates that evaluation of a reference produced an 

unexpected result. It is generated by operators (other than Enter) that evaluate 

references and reference chains if evaluation of an address couple parameter, SIRW, or 

IndexedWordDD produces an item that is neither a valid reference in the chain nor a 

valid target item that terminates the chain. The definitions of valid reference chains and 

valid target items vary according to the function of the operator. 

The interrupt is generated by vector and pointer operators that encounter unacceptable 

words in a vector, (source or destination) sequence, or (membership or translate) table. 

The P2 parameter is a proper reference to the offending target word. P1 is optionally the 

offending target word, except when the word has tag=2, it is changed to tag=0. 

Invalid Target can be considered a generic condition for the discovery of an unexpected 

word during reference evaluation. In many special cases, some other interrupt is 

generated instead. In particular, the Enter operators generate Missing PCW interrupts 

and some other operators generate a Touch interrupt if the target is an untouched DD. 

Source Boundary 

CVI ROI Repeat REXI(P1) ODI Es 

A Source Boundary interrupt is generated by TRNS, TUND, TUNU, TWSD, and TWSU 

operators that attempt to transfer data from the first element beyond the end of the 

source virtual segment. Other pointer operators that transfer characters from a source 

segment to a destination also generate this interrupt under the same circumstances. 

P2 is the source descriptor updated to the last+1 element of the segment. 

A Source Boundary interrupt usually reports an error, although under some 

circumstances the software may perform a service by supplying the rest of the missing 

source or terminating the transfer. 

4–18 6878 7530–007

Interrupts 

To cause the operation to continue with an operand source, the software must replace 

the source pointer argument on the stack below the interrupt AR by an operand. (It must 

also set P1.[38:1]:=1 prior to returning P1 with REXI, for those ClearPath MCP systems 

that interpret REXI as RETN.) For unconditional-transfer operators (TUND and TUNU, 

TRNS, TWSD and TWSU), the source-pointer argument is immediately below the length 

argument, which is the topmost operand below the interrupt AR. Note that there is a 

restart POW above the arguments. 

The operation may be terminated as described under "Destination Boundary" earlier in 

this section. 

Stack Underflow 

CVI POI( ) Abort-Here SI E 

Stack Underflow indicates that an operator attempted to pop an argument from an 

empty expression stack. The expression stack is the set of locations whose addresses 

are in the range {MAX(F+1,D[LL]+2) to S}. A Stack Underflow interrupt is generated 

when, in order to provide an argument to an operator, it is necessary to pop a word from 

the stack, but S is less than the lower bound. 

This interrupt is classified as an SI (even though it always results from a specific operator 

attempting to consume an argument from an empty expression stack), because no 

parameters are passed. 

Structure Error 

CVI ROI Abort-Here or Abort-Next ODI E 

A Structure Error interrupt is generated when the processor discovers an inconsistency 

in one or more of the critical data structures that the processor requires to execute 

operators: a stack, the ASD table, a page table, or the Scratch Pad. The interrupt usually 

indicates a serious failure of hardware or system software. Circumstances that result in 

interrupt generation are listed separately for each of the four types of structures, which 

are the following: 

• Stack Structure Errors 

• ASD Structure Errors 

• Page Structure Errors 

• Scratch Pad Errors (Libra 6xx and 7xx systems) 

Stack Structure Errors 

The following notation is used: 

Mem[a] = contents of memory word at address a 

Stk[d] = contents of current stack at displacement d 

HistLink = displacement computed from a history link 

EnvLink = address computed from an environment link 

.ASD_num = .stack_num or .seg_num for normal or pseudo link 

6878 7530–007 4–19

Interrupts 

The Enter, Exit, and aEVLK operations generate Structure Error interrupts under any of 

the following conditions: 

aEVLK: Mem[EnvLink] not entered ENVW 

Exit: Stk[D[LL]+1] not RCW 

Stk[F] not HISW 

Stk[HistLink+1] not {inactive ENVW, entered ENVW} 

Checking stack linkage words (HISW,ENVW, and RCW) only occurs whenever the word 

is accessed. Operators that update display registers may traverse part, but not 

necessarily all, of the environmental chain for the new environment. If the word is not 

the correct type, P2 is nearly always an SIRW that references it. 

ASD Structure Errors 

An ASD structure error is detected in the course of evaluating an ASD_number, which 

may be derived in any of several ways: 

1. Accessing data via a descriptor: the ASD_number is from the ASD_ref field of the 

DD. 

2. Accessing code via a PCW or RCW: the ASD_number is from the ASD_ref field of 

the control word. 

3. Evaluating an Environment Link: the ASD_number is from the env_link field of an 

SIRW or ENVW. 

4. Accessing the current stack: the ASD_number is derived from the SNR register. 

5. Accessing the current code segment: the ASD_number is in the PSN register. 

In all of these contexts, the following violations generate Structure Error interrupts: 

ASD1[ASD_number].tag < > 8: P2 is the absolute address of ASD1. 

ASD2[ASD_number].tag < > 8: P2 is the absolute address of ASD2. 

ASD1[ASD_number].address MOD 2**36 + offset >= 2**36: P2 is the reference 

whose evaluation caused the overflow. 

Page Structure Errors 

Violations of the invariants of paged array structure generate Structure Error interrupts: 

• ASD3 designated by indexed paged DD not unpaged IndexedDD: P2 is the absolute 

address of ASD3. 

• page-table word accessed by indexing unindexed paged DD or by reindexing ASD3 

not {unpaged unindexed DD, untouched DD}: P2 is an unpaged IndexedDD that 

references the page-table word. 

4–20 6878 7530–007

Scratch Pad Errors (Libra 6xx and 7xx Systems) 

A Scratch Pad Structure Error is reported when any of the following is detected: 

1. D[0] + 16 is not a DD (to Scratch Pad). 

2. Scratch Pad ASD has an error (structure error or MDE). 

3. Scratch Pad target word has an error (invalid tag or MDE). 

For all cases, P2 = 0 and P1 = 1. 

Undefined Operator 

Interrupts 

An Undefined Operator interrupt is generated for the attempted execution of an operator 

whose encoding is not valid in the context. 

Primary and variant encodings are expected in the normal succession of operators in the 

code stream, whether accessed sequentially or subsequent to branch or subroutine 

operators. Edit encodings are expected in the code stream following an enter single-edit 

operator or in a table designated by an enter table-edit operator. The ENDE, ENDF, and 

INSC operators are undefined following EXPU, EXSD, or EXSU; edit operators requiring a 

source are undefined following EXPU. 

Ordinarily, the resumption is Repeat EXIT (although useful resumption of the code 

stream is unlikely): 

CVI POI( ) Repeat EXIT ODI E 

If an edit operator was expected, the resumption is Abort-Here. The RCW points to the 

enter-edit operator and, for table edit, the table pointer is updated to point to the 

offending code syllable: 

CVI POI( ) Abort-Here ODI E 

Uninitialized Argument 


This interrupt is a special case of Invalid Argument; it is generated when an argument 

has a tag of 4 or 6 and fails to meet the type criteria for that operator. P2 is the offending 

argument. 

Systems that pass an argument with a tag of 4 or 6 as an interrupt parameter can report 

this condition as Invalid Argument. 

6878 7530–007 4–21

Interrupts 

Alarm Interrupts (Libra 6xx and 7xx Systems) 

Alarm interrupts are triggered by hardware fault detection. The interrupt RCW typically 

points to the operator sequence that was executing when the fault was detected; 

resumption is often not possible. 

Emulation Consistency Error 


This interrupt indicates that the processor detected a consistency error in its emulation 

code, not correctable by reloading the same level of emulation code. 

Emulation Error 

This interrupt indicates that the processor detected an error in its emulation code (e.g. 

tag not equal to 3, memory data error). Software should correct the emulation segment. 

Two Emulation Error conditions are defined, one for situations in which resumption is 

possible, and one for which it is not: 

Emulation Error - Here 

CVI ROI Repeat EXIT SI E 

Emulation Error - Lost 

CVI ROI Abort-Lost SI E 

If P2 is an integer, it is the absolute address of the emulation code word detected with a 

memory data error. If P2 is an IndexedDD, it references the emulation code word 

detected with some other error (probably tag). 

External Memory Write Error 

CVI POI( ) Abort-Lost SI E 

This interrupt indicates that the platform issued a Hard Fail response on a prior WEMW 

by the processor. 

Hardware Error 

This interrupt indicates that the processor detected an error in its own operation. 

Two Hardware Error conditions are defined, one for situations in which resumption is 

possible and one for which it is not: 

Hardware Error - Here 


4–22 6878 7530–007

Hardware Error - Lost 


Interrupts 

The P2 parameter for both repeat and abort hardware errors is formatted as follows: 

47:17 Zero 

30:3 Interrupt Count 

27:2 Stack Bounds Status 

25:3 Deferred Action Decompose 

22:3 Deferred Action Single Op 

19:4 Phase Count 

15:1 Zero 

14:3 Pass Count 

11:5 Zero 

06:7 Hardware Error Code 

Defined Hardware Error Codes 

Asynchronous Hardware Errors: 

11 MU MRT Job RF1 

12 MU MRT Job RF2 

13 MU Tag Double Hit RF1 

14 MU Tag Double Hit RF2 

15 MU Tag Ram Parity RF1 

16 MU Tag Ram Parity RF2 

17 MU MODS Queue Parity RF1 

18 MU MODS Queue Parity RF2 

19 MU AAT Compare 

1A MU SAL Address Parity 

1B MU Busy Table Parity 

EU Hardware Errors: 

40 Op queue parity 

41 Control store parity 

44 EBI parity 

45 EDA residue 

46 EDB parity 

47 EDB residue 

48 FA input parity 

49 FA input residue 

4A FA barrel parity 

4B FA shift residue 

4C EWD parity 

4D EWD residue 

6878 7530–007 4–23

Interrupts 

Other Synchronous Hardware Errors: 

50 WU HE: Address residue error (SAL) 

53 ACU Consistency error 

58 ACU HE: ASDAM write 

59 ACU HE: ASDAM multiple hit 

5A ACU HE: ASDAM read parity 

5B ACU HE: ASDAM page index parity 

5C MU HE: address residue 

DCU Hardware Errors: 

60 Micro-op Queue parity 

61 DLM Control Store parity 

62 Type parity 

63 “Y” MISC. parity / Input parity 

64 “DOD” VWI residue 

65 “DOD” ASD residue 

66 “X” MISC. parity / Divide residue 

67 “Z” MISC. parity 

68 “Z” VWI residue 

69 “Z” ASD residue 

6A DCU prefetch queue parity 

6E Micro-op Queue parity (op) 

CU Hardware Errors: 

70 Return Stack Consistency 

71 TOS Consistency 

72 Cache Read parity 

73 Control Store parity 

74 AT Misc parity 

75 Cache Misc errors 

76 Scanner Misc parity 

77 Parser Misc parity 

78 ACAM double hit 

79 TOS Misc parity 

7F Recovery Misc errors 

Invalid Address 

This interrupt indicates an attempt to address a word of memory that does not exist on 

the system. P2 is the reference which produced the invalid address. 

Two Invalid Address conditions are defined, one for situations in which the attempted 

access can be associated with a specific operator and one for which it cannot. 

Invalid Address - Here 


4–24 6878 7530–007

Invalid Address - Lost 


Loop Timer 

Interrupts 

This interrupt indicates an effectively infinite loop by an operator. It is triggered by 

expiration of a timer whose interval is sufficient for valid execution of any indivisible 

sequence of operators or one division of a divisible iterative operator. 

A Loop Timer interrupt indicates a processor fault, except that a program can induce the 

interrupt by attempting to evaluate an SIRW chain that loops or to traverse a historical 

chain (exit) that loops. 

The following operations are not subject to Loop Timer interrupt: 

HALT (when the Halt Boolean is true) 

STOP 

Idle state (waiting for external) 

WIPS TOD sync (waiting for IMS) 

Two Loop Timer conditions are defined, one for situations in which resumption is 


Loop Timer - Here 


Loop Timer - Lost 


For both situations, P2 is formatted identically to P2 for Hardware Error, except that 

P2 06:7 will be equal to 54. 

Memory Data Error 

This interrupt reports an attempt to read from memory a word that has an uncorrectable 

memory error. (No error may be reported regarding the prior contents of a memory word 

being overwritten by OVRD/OVRN or TWOD.) Single-bit read data errors are corrected by 

hardware and will not be reported by an interrupt. 

Two Memory Data Error conditions are defined, one for situations in which resumption is 


Memory Data Error - Here 


Memory Data Error - Lost 


6878 7530–007 4–25

Interrupts 

P2 contains the absolute address in field [35:36]; field [46:11] is zero. Bit 47 true 

indicates the address is to I/O space. 

For only Memory Data Error-Lost, P1 may be non-zero, indicating a specific failure unique 

to REMW accessing external memory: 

P1 = 1 – cause was Bus MDE 

P1 = 2 – cause was Hard Fail response from platform 

SLC Interface Error 

This interrupt indicates that the processor detected an error with the Second Level 

Cache interface. 

Two SLC Interface Error conditions are defined, one for situations in which resumption is 


SLC Interface Error - Here 


SLC Interface Error - Lost 


For both situations, P2 is formatted identically to P2 for Hardware Error, except that 

P2 06:7 will be one of the following: 

1C SLC Protocol 

1D SLC Ctrl parity 

1E SLC Purge parity 

55 MU memory jobs busy 

56 CU memory jobs busy 

57 MU and CU memory jobs busy 

Asynchronous Interrupts 

Asynchronous interrupts are independent of the code stream and usually occur due to 

the expiration of a timed interval. Software must periodically set an Interval Timer and a 

Run Timer, and recognize the corresponding asynchronous interrupt that occurs when 

either timer expires. 

Interval Timer 

Note: Libra 4000 systems do not support this interrupt. 

CVI POI( ) Continue EXIT SI S 

There is one Interval Timer per processor whose value indicates the amount of time a 

processor can execute without reporting an interrupt. An expired Interval Timer signals 

software to initiate a move stack operation. This interrupt is masked by control state. No 

parameters are passed to this interrupt. 

4–26 6878 7530–007

Interrupts 

An Interval Timer is set by the Set Interval Timer (SINT) operator. If the Interval Timer 

decrements to zero, or is explicitly set to zero, an Interval Timer interrupt is reported to 

software. 

Any asynchronous or external interrupt causes the Interval Timer for the processor 

reporting the interrupt to be disarmed. 

Run Timer 

CVI POI( ) Continue EXIT SI S 

There is one Run Timer per processor. Each Run Timer value indicates the amount of 

time a processor can execute before software sets the value again. An expired Run 

Timer usually indicates a software error, typically excessive time spent in control state. 

This interrupt is not masked by control state. No parameters are passed to this interrupt. 

Note: Libra 4000 systems do not support this interrupt. 

The Running Indicator (RUNI) operator arms the Run Timer to 30 seconds. If the time 

value elapses before the next RUNI invocation, a Run Timer interrupt is reported to 

software. 

The Run Timer stops decrementing when a processor is halted and resumes 

decrementing if that processor is continued. 

If a Non-maskable Interrupt condition is detected at the same time, the Run Timer takes 

precedence over NMI. In this case, the Run Timer CVI is reported and the Non-maskable 

CVI is dropped. A Maskable IPI is also dropped if one is pending at this time (the 

corresponding IRR bit is reset). 

External Interrupts 

External interrupts are generated to report occurrences outside a processor, such as 

communication from another component of the system. 

Note: The only external interrupts handled by the CPM in the Libra 4000 systems are 

those that other operational modules use to get the attention of the CPM. These are 

handled internally by the CPM and the system software is never invoked to handle an 

external interrupt. 

Non-maskable Interrupt 

CVI ROI Continue EXIT SI S 

The Non-maskable Interrupt is used to interrupt a processor out of control state, 

presumably because it failed to respond to a Maskable Interrupt. A running processor 

that fails to respond to a Maskable External Interrupt is normally looping in control state. 

In response to a Non-maskable Interrupt request, a processor reports this interrupt to 

software. P2 is the proc ID of the processor that issued the NMI, which used the APIC 

vector field to hold that ID. 

6878 7530–007 4–27

Interrupts 

If a Run Timer interrupt condition is pending, but NMI occurred just ahead of the Run 

Timer, NMI takes precedence over the Run Timer. In this case, the Non-maskable CVI is 

reported and the Run Timer CVI is dropped. A Maskable IPI is also dropped if one is 

pending at this time (the corresponding IRR bit is reset). 

Maskable External Interrupts 

A Maskable External Interrupt (MEI) applies to Libra 6xx and 7xx systems only. It refers 

to the interrupt reported by an IP that has a corresponding interrupt request in the 

Interrupt Request Register (IRR) of its Local APIC. A MEI is a type of External Interrupt, 

which differs from a CVI or OVI condition because procedure entry does not occur 

through a reference in the E-mode Interrupt Vector (via ASD 3) and the Interrupt Count 

does not increment. A MEI is also unique in passing exactly one word as an interrupt 

parameter. 

Note: The only external interrupts handled by the CPM in the Libra 4000 systems are 

those that other operational modules use to get the attention of the CPM. These are 

handled internally by the CPM and the system software is never invoked to handle an 

external interrupt. 

Three MEI classes are defined, based on the defined interrupt requests in the IRR: 

I/O Interrupt (IRR bits 16-215) 

MIP Interrupt (IRR bit 216) 

Maskable IPI (IRR bit 217) 

Note that the Local APIC of an idle or halted IP still accepts interrupt requests. These 

interrupts remain pending in the IRR until the IP is started or continued, and either 

transitions to normal state or executes a PAUS or IDLE. If an idle or halted IP is removed 

from the partition, pending interrupts in its IRR are lost. 

Entry Points 

For each MEI class, software defines a corresponding entry point in the D[0] stack. Each 

entry point is a PCW to an interrupt procedure declared at a fixed D[0] offset. 

MEI Class D[0] Offset 

I/O Interrupt 4’E’ 

MIP Interrupt 4’C’ 

Maskable IPI 4’F’ 

To report a MEI, the IP maps a given interrupt request number to a MEI class and 

directly enters a procedure whose PCW resides at the D[0] offset reserved for that 

interrupt class. The interrupt request number is pushed as an integer parameter to the 

target procedure. 

When reporting a MEI to software, the IP resets the IRR bit that corresponds to the 

interrupt request. 

4–28 6878 7530–007

Interrupts 

If the IRR indicates other interrupts are pending, software may process them via the 

External Branch (EXTB) operator, but only from the target procedure for a MEI. Thus, 

EXTB allows software to process multiple interrupt requests during a single MEI. 

The IP will generate a Missing PCW interrupt if the D[0] offset for a given entry point 

does not contain a PCW. 

I/O Interrupt 

When an I/O interrupt is reported to software, the interrupt vector parameter to the 

target procedure identifies the PCI slot that generated the interrupt. 

MIP Interrupt 

The MIP to host interrupt informs software that Server Control wants to communicate 

information via the partition mailbox. 

Maskable IPI 

The Maskable IPI allows a processor to interrupt another processor in the same MCP 

partition. Global MCP state determines what action is taken by the destination IP (i.e. 

answer a dialing processor, become a dump follower, change stack). 

Interrupt Vector 

An interrupt is generated by invoking the aINTE action with an interrupt reference (SIRW) 

constructed by the processor. The components of the SIRW are: 

stack_num = 3 

stack_disp = 1 for CVI, 50 for OVI 

pseudolink = 0 

offset = value defined for particular interrupt 

Each CVI has a single fixed offset. 

Each OVI has a different offset for each operator: 

primary: opcode*4 - 511 + OVI_number 

variant: opcode*4 + 513 + OVI_number 

An OVI_number is assigned generically for each OVI condition: 

0: False Assertion 

0: Arithmetic Overflow 

1: Arithmetic Underflow 

2: Integer Overflow 

2: Vector Arithmetic Exception 

3: Unimplemented Operator 

6878 7530–007 4–29

Interrupts 

The following lists define the offsets for all interrupts except Unimplemented Operator, 

which is always OVI slot 3 for the operator to be trapped. Offset values are shown in 

decimal and (hex). Unnamed offsets are unused. 

CVIs: stack_disp =1 

1 (001) Touch CSD 

2 (002) Missing PCW 

3 (003) Absent Data Segment 

4 (004) Absent Code Segment 

5 (005) Touch Reference 

6 (006) Touch Load 

7 (007) 

8 (008) Destination Boundary 

9 (009) Source Boundary 

10 (00A) 

11 (00B) Block Exit 

12 (00C) 

13 (00D) 

14 (00E) Invalid Target 

15 (00F) Invalid Address - Here 

16 (010) Memory Data Error - Lost 

17 (011) Invalid Argument or Parameter 

18 (012) Bounds Error 

19 (013) 

20 (014) Structure Error 

21 (015) Invalid Operator 

22 (016) Invalid Access 

23 (017) Undefined Operator 

24 (018) Uninitialized Argument 

25 (019) External Memory Write Error 

26 (01A) 

27 (01B) Non-maskable External 

28 (01C) Emulation Error - Here 

29 (01D) Emulation Error - Lost 

30 (01E) Memory Data Error - Here 

31 (01F) SLC Interface Error - Here 

32 (020) Invalid Address - Lost 

33 (021) Stack Overflow 

34 (022) Stack Underflow 

35 (023) Invalid Code Word 

36 (024) Loop Timer - Lost 

37 (025) Hardware Error - Lost 

38 (026) 

39 (027) SLC Interface Error - Lost 

40 (028) Running Timeout 

41 (029) Loop Timer - Here 

42 (02A) Hardware Error - Here 

43 (02B) 

4–30 6878 7530–007

44 (02C) Interval Timer 

45 (02D) Emulation Consistency Error 

46 (02E) 

47 (02F) 

48 (030) 

OVIs: stack_disp = 50 (0032) 

1 (001) ADD Arithmetic Overflow 

5 (005) SUBT Arithmetic Overflow 

9 (009) MULT Arithmetic Overflow 

10 (00A) Arithmetic Underflow 

13 (00D) DIVD Arithmetic Overflow 

14 (00E) Arithmetic Underflow 

17 (011) IDIV Arithmetic Overflow 

19 (013) Integer Overflow 

21 (015) RDIV Arithmetic Overflow 

22 (016) Arithmetic Underflow 

23 (017) Integer Overflow 

27 (01B) NTIA Integer Overflow 

31 (01F) NTGR Integer Overflow 

61 (03D) MULX Arithmetic Overflow 

62 (03E) Arithmetic Underflow 

305 (131) SNGT Arithmetic Overflow 


309 (135) SNGL Arithmetic Overflow 


991 (3DF) BCD Integer Overflow 

1023 (3FF) DBCD Integer Overflow 

1025 (401) ASRT False Assertion 

1051 (41B) NTTD Integer Overflow 

1055 (41F) NTGD Integer Overflow 

1082 (43A) NORM Arithmetic Overflow 

1085 (43D) AVER False Assertion 

1291 (50B) SUM Vector Arithmetic Exception 

1295 (50F) SUMA Vector Arithmetic Exception 

1299 (513) DOT Vector Arithmetic Exception 

1303 (517) DOTX Vector Arithmetic Exception 

1307 (51B) SEQ Vector Arithmetic Exception 

1311 (51F) POLY Vector Arithmetic Exception 

1423 (58F) CPVS Vector Arithmetic Exception 

1431 (597) VPV Vector Arithmetic Exception 

1435 (59B) VMV Vector Arithmetic Exception 

1439 (59F) VMVN Vector Arithmetic Exception 

1443 (5A3) VTV Vector Arithmetic Exception 

1447 (5A7) VOV Vector Arithmetic Exception 

1451 (5AB) VUV Vector Arithmetic Exception 

1455 (5AF) VPS Vector Arithmetic Exception 

1459 (5B3) VTS Vector Arithmetic Exception 

Interrupts 

6878 7530–007 4–31

Interrupts 

1463 (5B7) VPVS Vector Arithmetic Exception 

1467 (5BB) VSPV Vector Arithmetic Exception 

4–32 6878 7530–007

Section 5 

Operator Set 

This section applies to all Level Epsilon systems. Most operators are available in all 

ClearPath MCP systems; see Appendix A to identify those operators introduced in Level 

Epsilon systems. 

General Information 

Operators and Code Streams 

An operator is composed of an op code and up to four parameters. Op codes are 

typically one syllable and parameters, if any, are in the syllables following the op code. 

Op code and parameter mapping into syllables varies; operator formats are explicitly 

specified in this section and in Appendix A. (The term parameter is used in operator 

descriptions to describe items from the code stream; the term argument is used for 

items from the stack.) 

A code stream is considered to be a sequence of syllables fetched without regard to 

word boundaries, except for the special case of LT48 and MPCW operators. 

In diagrams specifying op code and parameter interpretation, the operator name is used 

to represent its op code value. (Op code values are specified in Appendixes A and C.) 

Vertical bars (|) denote syllable boundaries and dotted vertical lines (:) denote parameter 

boundaries not corresponding to syllable boundaries. 

The following diagram shows a three-syllable operator, including two single-syllable 

parameters. 

 

Operator op 

P1 P2 

format: name 

 

The next diagram shows a three-syllable operator, two syllables of which is a single 

parameter: 

 

Operator op 

P1 

format: name 

 

6878 7530–007 5–1

Operator Set 

The final diagram shows a three-syllable operator including two parameters that are 

mapped into two syllables. P1 is 3 bits and P2 is 13 bits. 

 

Operator op : 

P1 : P2 

format: name : 

 

: 

3 : 13 

Primary, Variant, and Edit Operators 

Depending on context, there may be several interpretations of an op code syllable: 

• Primary op codes are represented in a single syllable. 

• Variant op codes are represented by two syllables of which the first is the primary 

operator VARI. 

• Edit op codes are found in special tables (specified as an argument to an Enter Table 

Edit operator, TEED or TEEU) or in the code stream immediately following an Enter 

Single Edit operator (EXSD, EXSU, or EXPU). 

Common Actions 

The concept of a common action is used in this document for a function that is common 

to several operators. Common actions are defined to effect economy by reducing 

repetition, to improve precision, and to provide a convenient reference for citation. 

Common actions are given three- and four- letter names like operators with a prefix of a, 

as in aACCE. It should be emphasized that a common action specification is a rhetorical 

device used to specify operators; it does not define an operator. 

Order of Execution 

Operators from the code stream are executed in sequence until the code stream is 

redirected by a branch, enter, or exit operation. The processor can perform individual 

operations in parallel and execute operators out of order, as long as the effective order of 

the program is preserved. For example, any value fetched or consumed by an operator 

must be the value stored or produced by the closest predecessor operator affecting that 

memory or stack location. These store-before-read and produce-before-consume 

restrictions apply within the code stream on a single processor, not necessarily between 

code streams on separate processors. Two processors cannot share the same stack at 

the same time; therefore, produce-consume relationships cannot apply. To enforce a 

store-read sequence between processors, the processes must explicitly use 

synchronizing operations. 

There are exceptions to the store-read sequence requirement when the words being 

read can have been captured by the processor as hidden optimization state; see 

"Program Restrictions Due to Hidden State" at the end of this section. 

5–2 6878 7530–007

Interrupts and Resumption 

Operator Set 

When an operator cannot be performed or completed according to the definition of its 

normal operation, an interrupt is generated, the operator is aborted, and a procedure of 

the operating system is entered. The interrupt procedure is provided enough information 

to determine the circumstances and take the appropriate action. 

Operator interrupts can generally be characterized as error reports or service requests, 

although the distinction is blurred. Errors can sometimes be corrected or used to induce 

special actions and services can be limited or denied. 

Service requests are implicit in most operations that can encounter these situations; only 

occasionally are they explicitly pointed out in this document. 

When a service request is honored (for example, a segment is made present in memory 

upon demand) or an error is accommodated, the code stream is resumed as the interrupt 

procedure is exited. Depending upon the circumstances, the interrupted operator is 

repeated or its successor proceeds. If the service cannot be performed or the error is 

unrecoverable, the interrupted code stream cannot be resumed. These resumption 

characteristics vary with interrupt type and circumstances. 

For more information on interrupts, see Section 4. 

Preconditions and Invariants 

Restart Mode 

Throughout this manual, restrictions are defined on structures, argument types, values, 

and so forth. These statements typically include words such as must, required, cannot, 

or valid; they define the preconditions and invariants for the correct functioning of the 

operators. 

In many cases, the processor detects violations of these restrictions and generates 

interrupts when violations occur. Some constraints are not enforced. Not all the checks 

applicable to the operator are mentioned in every operator description; many are 

described generally for a class of operator. 

When an interrupted code stream is resumed by repeating the interrupted operator, 

most operators can begin again to perform their normal function. Such operators are said 

to resume in initial mode. Sometimes, however, the resuming operator may not be able 

to start over from the beginning; for example, it might expect a different stack 

configuration or make different assumptions about some system state. For these 

operators, a restart mode is defined. 

The fact that an operator resumes in restart mode provides one bit of information; when 

more is required, the interrupt mechanism leaves a word on the stack for the restarted 

operator to consume as an extra argument. 

Restart mode occurs through accidental entry, as well as interrupts. 

6878 7530–007 5–3

Operator Set 

Restart mode is indicated by the rs bit in the stack lineage above an activation record; 

the bit is set as the procedure is entered by the interrupt mechanism or by accidental 

entry. The setting of the bit in these cases is determined by the operator and 

circumstances of the interruption. For explicit programmatic procedure entry, the bit is 

always reset. When an exit operator finds the bit set, the next operator executed is 

begun in restart mode. 

In general, the information implied by the use of restart mode must be preserved until 

the operator is completed. Once an operator has been resumed in restart mode, any 

subsequent interruption and resumption of the same operation must use restart mode. 

For details regarding the use of restart mode, see "Restart Configuration" in Section 4. 

Operator Applicability 

Most of the operators defined in this manual are generally applicable; compilers may use 

them in programs written by and for end users. Some operators are restricted to special 

uses or are being phased out; several classes of operators are indicated in this manual: 

1. Unrestricted: these operators are available for general use in user and system 

code files. Those operators that are new in Level Epsilon can be used only in code 

files to be run on such systems; most unrestricted operators may be used in 

"universal" code files or those that run in all supported systems. 

2. Obsolete: these operators have been unrestricted, but they are no longer 

necessary and should not be used. 

3. Partially restricted: these operators have some application in user programs only 

in special situations. The partial restriction applies because the operators are 

dangerous if abused, but there is no cost-effective alternative to their use in some 

user-program constructs. 

In addition to the partially restricted operators that are explicitly identified, there are 

restrictions on the application of other classes of operators that are not individually 

noted: 

• Logical, bit-field, and similar operators must be applied with care to data types 

other than operands. 

• Operators containing address couples must be used to reference only data 

within the program domain and of the appropriate type. (Delta values must be 

within the range of the activation record; Lambda must be in {1 to LL} in user 

programs, although it is software convention, rather than the architecture, that 

places user code segment dictionaries at lex level 1 rather than 0.) 

• Any operator that can consume an arbitrary top-of-stack input must be used only 

against items in the expression stack and never to consume an original DD or 

stack-linkage word. 

All partial restrictions are enforced by the compilers according to convention. 

4. Restricted: these operators do not appear in user programs; they are dangerous 

and their use is restricted to low-level code in the operating system. (See 

Appendix E.) 

5–4 6878 7530–007

Operator Set 

Some operators, not otherwise restricted, are obsolete either because they have been 

superseded by more suitable operators or because they are deemed not to be costeffective. 

Obsolete operators should not be used by compilers; there are better 

constructs on all supported systems. 

Obsolete and restricted are noted in the individual operator specifications and are flagged 

in Appendix C. 

Expression Stack Control 

Most operators require items from the top of the expression stack and/or leave their 

results on top of the stack. Stack items required by operators are called arguments. They 

are normally consumed; that is, they are used and deleted from the stack. For 

consistency and brevity, this manual always defines arguments as deleted; any 

argument not consumed is defined as becoming an output. 

Only the double precision operand (tag-2 pair) is treated in the expression stack as a 

single two-word item. All other data types are treated as single word items when 

encountered as arguments and are pushed or popped as single words. 

Processors can capture up to seven expression-stack items internally; the remainder is in 

memory in the current stack. The S register designates the topmost word in the memory 

stack; the processor automatically moves data between memory and the registers as 

necessary. The value of S is independent of any argument registers; that is, the register 

contents must be actually pushed into memory in computing S. 

Items in registers are not addressable with address couples; a PUSH or enter operation 

is required to move the expression stack into the activation record. 

The point at which Stack Overflow occurs is dependent upon the number of expressionstack 

registers and how they are used; the interrupt need not occur on the operator 

whose output moved virtual S beyond the stack. It is appropriate to consider this 

interrupt an asynchronous service exception. 

Top-of-Stack Push Operations 

Operators that produce top-of-stack results must push them, in order, onto the 

expression stack. Such a push operation only writes the memory stack if there is not 

enough room in the processor's TOS registers. If the topmost word of the stack is 

reached in a push operation, a Stack Overflow interrupt is generated. The interrupt does 

not occur between the two words of a double precision item. If it occurs after the 

implicit Mark Stack through the Enter operation of an interrupt generation or accidental 

entry, the entry’s incipient activation record is below the stack overflow frame, and the 

exit from that frame is forced to resume the entry by a HISW action status. 

In processor state, a double precision operand is treated as a 96-bit operand with a single 

tag equal to two. When a tag-2 item is pushed onto the stack, the high order and low 

order words are written in that order, both with tags of two. 

6878 7530–007 5–5

Operator Set 

Top-of-Stack Pop Operations 

Any operator that requires a stack argument must pop it from the expression stack. Such 

a pop operation only reads the memory stack if there are not enough items in the 

processor's TOS registers. If the word at the top of the memory stack has tag equal to 

two, the word below is also popped. The top and next words are taken as the second 

and first words of a double precision operand. (Note that because argument items may 

be either single or double words, multiple arguments must be accessed by popping 

them in order, from the topmost down.) 

Operands, references, and other unprotected items that have been explicitly pushed into 

the addressing environment can be consumed as arguments, in which case, they 

automatically migrate back into the expression stack. Protected items such as original 

DDs, POWs, and stack linkage words do not migrate in this way, however PCWs do so 

that they can be deleted. 

Stack Underflow is detected if a pop operation attempts to consume the stack linkage. 

Ideally, the lowest address that can be popped should be MAX(F+1,D[LL]+2) to protect 

both entered and incipient ARs. However, most Libra systems enforce only one of the 

checks, comparing S to F. 

Stack-State Transformation 

Stack state includes the top-of-stack items and the stack-addressing registers. Most 

operators take arguments from and place results on the stack without affecting any 

register except S. 

Top-of-stack transformations are shown by diagrams that display inputs and outputs in 

order from top downward: 

Input items Output items 

(arguments) (results) 

The effects of the transformation is that all the inputs are consumed and all the outputs 

are created. "Null ==>" and "==> Null" indicate that the operator has no inputs or outputs, 

respectively. There is an implicit variant. The item that was on the stack below the 

lowest input (if any) remains on the stack below the lowest output (if any), unaffected by 

the top-of-stack transformation of the operator. The input items are shown for the initial 

mode of the operator; some operators have additional stack input arguments in restart 

mode. 

Initial stack items are designated Id: type(interpretation), where Id and interpretation are 

optional. Type may be a data type, as defined in Section 2 or a list of such types; any 

indicates no type restriction. An Id, if included, is a distinguishing name indicating how 

the item is to be used and/or establishing a reference for the final stack state. The 

generic names TOS and TOS2 represent the top-of-stack and second-from-top items. 

Interpretation is shown if the operator applies one of several possible interpretations of 

the type. 

5–6 6878 7530–007

Operator Set 

Final stack items are designated similarly. An Id or Id' indicates that the result is the 

named argument in identical or modified form, respectively; the modified argument has 

the same type unless another type is shown. 

A simple description of inputs into outputs is inadequate for operators that modify stack 

linkages and registers. Schematic stack-state transformation diagrams illustrate these 

operations. 

Expression Stack Treatment of Word Extension 

General Use 

The following states the general nonreference treatment of extensions for top-of-stack 

arguments and results, including targets of evaluation. The behavior of many specific 

operators or operator groups is defined later in this section. 

Generally, a single word top-of-stack argument with a nonzero extension, but not used 

as a reference, treats it as a 4-bit entity somewhat like a second tag, except that it has 

no type implications. 

1. Result extension: If an operator selects the argument's tag as the result tag, it also 

selects the argument's extension. If an operator selects an argument or target as the 

result, or only modifies the tag of an argument (for example, STAG) or target (for 

example, aFOP), it generally preserves the extension. The definitions of SASF, SASP, 

SSTN, and SEXT requires each to change the extension. In general, all other cases 

zero the result extension. 

2. Result value: If an operator includes the argument's tag as part of function's bit 

vector (e.g. SAME), it includes the argument's extension also. The definitions of 

GASF, GASP, GSTN, and GEXT requires each to use the extension. In general, all 

other cases ignore the argument's extension in generating the non-extension part of 

the result . 

Double precision top-of-stack arguments follow the above guidelines for the most 

significant word. The extension of the least significant word should never be used. 

Descriptor Interpretation 

Most of the data and all the code in ClearPath MCP systems reside in memory 

segments described by VSDs. The address of a particular memory word is computed by 

adding an index to the base address of an actual segment. For data, the index and the 

reference to the base of the actual segment are combined into a single item, an 

IndexedDD. 

The word referenced by an IndexedDD is located by adding the word index and the base 

address of the actual segment. The word index in an IndexedDD must be verified against 

the length field in the designated ASD. 

For the referenced word to be accessed, the segment must be present. The presence 

indication is in the ASD. Any attempt to access data in a nonpresent segment results in 

an Absent Segment exception. 

6878 7530–007 5–7

Operator Set 

Code is normally referenced via a PCW. (For edit-mode code executed as a result of an 

enter-table-edit operator, the reference is an IndexedDD.) The Make PCW operation 

replaces the address couple in the PCW skeleton with an ASD_number, so the PCW is a 

complete reference, analogous to the IndexedDD. Any attempt to enter or branch to a 

non-present code segment results in an Absent Segment exception. 

Computational Operators 

Operators in this group are loosely termed computational operators because they take 

arguments directly from the stack and leave some form of result on top of the stack. 

Computational operators will not evaluate references; their arguments must be items on 

the stack initially. Required parametric values may be static code parameters or dynamic 

stack arguments. 

Numeric Operand Interpretation 

Operators in this group act on single or double precision operands interpreted as integers 

or floating-point numbers. 

The extension and the leftmost bit of an operand play no role in numerical computation. 

With certain exceptions defined for NTGR, numerical computation and type transfers 

leave bit 47 in an undefined state. 

Representable Values 

Consider the set V of all representable values. V is a subset of the rational numbers. An 

element of V can be represented by a 3-tuple (mi, mf, e), where: 

mi is the integer part of the mantissa 

mf is the fractional part of the mantissa 

e is the exponent 

The symbols +, -, *, / are used to denote the usual arithmetic operations on rationals and 

the symbol ** denotes exponentiation. 

Let p = maximum number of octal digits in mi; 

d = maximum number of octal digits in mf; 

q = maximum number of octal digits for the exponent; 

m = mi + mf * 8**(-d) 

The set M of representable mantissas is 

M = { m : 0

Operator Set 

For p=13, d=0, q=2, e=0: V=I, the set of representable single 

precision integers. 

p=13, d=0, q=2: V=S, the set of representable single 

precision floating-point values. 

p=13, d=13, q=5, e=13: V=Id, the set of representable double 

precision integers. 

p=13, d=13, q=5: V=D, the set of representable double 

precision floating-point values. 

A representation is defined to be normalized if |mi| >= 8**(p-1) or if mi = mf = e = 0. 

That is, a normalized representation is either zero in all components, or is non-zero in the 

high-order octade of the mantissa. The set Vn of normalized values is thus defined as a 

subset of V: 

Vn = { v : v in V and ( 8**(p-1)

Operator Set 

The notion of digit significance can be quantified in terms of the value of a "1" in the 

lowest-order digit of the mantissa. The unit value for any representation v = m * 8**e in 

V is u(v) = 8**(e-d). A rounding function must choose a value of v that is not more than 

u(v)/2 different from the value of k. A truncation function must choose a value of v such 

that |v|

Rounding Function R 

Operator Set 

A rounding function R is defined below; R selects the element of V' that is closest to the 

desired value. If two elements of V' are equally close to the desired value, the element 

larger in absolute value is chosen. 

The rounding function partitions the real line into intervals and maps each interval onto a 

representative element of that interval. 

Example: 

Consider 

v = m * 8**e in V’ (with (mi,mf,e) in normal form); let c = 1/2 * 8**(- d). 

Then the intervals and their representative values are defined so that v is the 

representative value for all x > 0 in the interval 

0 < lb(v) 1 - 8**q} 

 

 

and ub(v) = (m+c) * 8**e. 

v is the representative value for all x < 0 in the interval 

-ub(-v) < x

Operator Set 

R: K V union { TooSmall, TooBig } 

let alpha = c * 8**(1 - 8**q) 

omega = (8**p - c) * 8**(8**q - 1) 

 

TooBig omega

Magnitude Round-to-Integer Function Ri 

Operator Set 

In order to integerize a value by rounding the absolute value, a special rounding function 

is necessary. This function, Ri, is analogous to R, but integer elements of V are chosen 

instead of elements of V'. 

Ri: K V union { TooBig } such that 

for every k in K, with integer v 

and omega = 8**(d+p) - 1/2, 

 

TooBig omega

Operator Set 

Algebraic Round-to-Integer Function Rai 

A second special rounding function, Rai, is defined to round an algebraic (signed) value to 

an integer. This function is the same as Ri, except that if two integers are equally close 

to the desired value, the algebraically larger integer is chosen. 

Rai: K V union { TooBig } 

for every k in K, with integer v 

and omega = 8**(d+p) - 1/2 

 

TooBig omega

Truncation Function T 

Operator Set 

The truncation function T chooses the value in V' with the largest absolute value not 

greater than the absolute value of the desired value k. T partitions the real line into a 

different set of intervals from those of R. 

Consider v = m * 8**e in V' (with (mi, mf, e) in normal form). Then the intervals and their 

representative values are defined such that: 

v is the representative value for all x > 0 in the interval 

0 < v

Operator Set 

Magnitude Truncate-to-Integer Function Ti 

In order to integerize a value by truncation, a special integer truncation function is 

necessary. This function, Ti, is analogous to T, but integer elements of V are chosen 

instead of elements of V'. 

Ti: K V union { TooBig } such that 

for every k in K with integer v 

and omega = 8**(p+d): 

 

TooBig omega

Normalization Function N 

Operator Set 

A normalization function, N, is needed to put results in normalized form. Because Vn is a 

subset of V' and every element of V has a unique representation in V', every 

normalizable element of V has a unique normalized representation in Vn. 

N: V Vn union { TooSmall } such that 

for alpha = 8**(p-1) * 8**(1 - 8**q) = 8**(p - 8**q), 

 

v (normalized) alpha

Operator Set 

Approximation Functions 

For arithmetic operations, a class of rounding functions R has been defined to map the 

set of arithmetic results, K, into the set 

V union {TooBig, TooSmall} 

The definition of R does not depend on the fact that K is a set of rational numbers; the 

same function R can be applied to map the set K* onto the result set, where 

K* = { k : k = f(x) or k = f(x,y), x,y in V 

and in the domain of f } 

and f is a computable function of one or two variables. 

As shown, R(f) could be used to define the correct value of the function. However, it 

may be impractical to evaluate mathematical functions with sufficient precision and 

accuracy to make such a definition useful. Instead, approximations are computed; rather 

than defining one correct result, the set of results that are sufficiently close to the 

correct one are defined. 

Informally, the set of approximate values Aj(x) to the true value x includes those values 

that differ from x by no more than j times the value of the low-order bit, if the mantissa is 

a normal representation of x. 

The set Aj(x) contains at most 2j+1 values near x. There is a nearest number, which is an 

element of Aj(x), defined by the Rounding function R(x). The other elements are the 

subset of v in V such that R(x + h*u(v')) = v, where v' is the representation of v in normal 

form, u is the unit function, and h is a nonzero integer in the range {-j to j}. It is possible 

for Aj(x) to contain only TooBig or TooSmall or to contain one of those values and up to 2j 

representable values. 

The processor will choose an element of Aj(x) as its representation of x. Any element is 

acceptable. If TooBig or TooSmall is chosen, an Exponent Overflow or Exponent 

Underflow exception is generated, respectively. 

Aj is a set-generating function based on the class of rounding functions R. The sets of 

single and double precision approximations ASj(x) and ADj(x) are defined by the specific 

rounding functions RS and RD, respectively. 

Note: AS0(x) = {RS(x)} and AD0(x) = {RD(x)} 

If f(v) equals zero for some representable value v in V, then Aj(f(v)) equals zero. For 

example, square root must return zero for the argument 0. 

5–18 6878 7530–007

Numeric-Interpretation Operators 

Operator Set 

The operators in the following groups interpret operands numerically as a primary part of 

their function; numeric interpretation also occurs as some part of the function of 

operators in other groups. 

For dyadic operators, the second from top of stack operand is denoted x and the top 

operand y. Unless a diagram is included in the operator definition, dyadic operators effect 

the following transition. Note that real interpretation includes integers as a subset. 

 

 

y: opnd(real) 

Top-of-stack 

 

transformation: 

x: opnd(real) opnd(real) 

 

 

For monadic operators, the top of stack operand is denoted x. 

 

Top-of-stack 

x: opnd(real) opnd(real) 


 

Arithmetic Operators 

Arithmetic operators are dyadic, except for NORM, which is monadic. 

Dyadic operators generate a single precision result if both operands are single precision 

and a double precision result if either or both operands are double precision. Where 

required, single precision is extended to double precision prior to the operation by 

appending a second word of all zeros; note that the numeric value of the operand is not 

changed. 

Let AxB signify the Cartesian product of two sets A and B. The definition for the 

following arithmetic operators deals only with the domains SxS and DxD. Since S is a 

subset of D, the domains SxD and DxS are considered special cases of DxD. 

The ranges of the operators are subsets of V, depending upon the values of p, d, and q 

and upon the rounding or truncation function invoked by the particular operator. If the 

result is TooSmall or TooBig, an interrupt appropriate to the operation is generated. 

6878 7530–007 5–19

Operator Set 

ADD 

ADD requires two operands on top of the stack. The numeric values of the two operands 

are algebraically added and rounded, and the result is left on top of the stack. 

or 

ADD: S x S S union { TooBig } 

such that x ADD y = RS(x+y) for x,y in S 

D x D D union { TooBig } 

such that x ADD y = RD(x+y) for x,y in D but 

not x,y in S. 

For x,y in S or D, 0 < |x ADD y| < alpha cannot occur, so Exponent Underflow is never 

generated by ADD. If both x and y are single_integers and the absolute value of the sum 

is less than 8**13, then the result is a single_integer. 

SUBT 

SUBT requires two operands on top of the stack. The numeric value of the top item is 

algebraically subtracted from the numeric value of the second item and rounded and the 

result is left on top of the stack. 

or 

SUBT: S x S S union { TooBig } 

such that x SUBT y = RS(x-y) for x,y in S, 


such that x SUBT y = RD(x-y) for x,y in D but 

not x,y in S. 

For x,y in S or D, 0 < |x SUBT y| < alpha cannot occur, so Exponent Underflow is never 

generated by SUBT. If both x and y are single_integers and the absolute value of the 

difference is less than 8**13, then the result is a single_integer. 

MULT 

MULT requires two operands on top of the stack. The numeric values of the two 

operands are algebraically multiplied and rounded and the result is left on top of the 

stack. 

or 

MULT: S x S S union { TooSmall, TooBig } 

such that x MULT y = RS(x*y) for x,y in S, 

D x D D union { TooSmall, TooBig } 

such that x MULT y = RD(x*y) for x,y in D 

but not x,y in S 

If both x and y are single_integers and the absolute value of the product is less than 

8**13, then the result is a single_integer. 

5–20 6878 7530–007

MULX 

Operator Set 

MULX requires two operands on top of the stack. Any single precision operand is 

extended to double precision before the numeric values are algebraically multiplied and 

rounded. The double precision result is left on top of the stack. 

 

 


Top-of-stack 

 


x: opnd(real) dp(real) 

 

 

MULX over SxS is equivalent to a combination of XTND over S and MULT over DxD. 

MULX over DxD is equivalent to MULT over DxD. 

DIVD 

DIVD requires two operands on top of the stack. The numeric value of the second item 

is algebraically divided by the numeric value of the top item and rounded, and the result 

is left on top of the stack. If the divisor (top of stack operand) equals zero, a Divide by 

Zero exception is generated; if the code stream is resumed, the result of the operator is 

a zero of appropriate type (single or double precision). 

or 

DIVD: S x S S union { TooSmall, TooBig } 

such that x DIVD y = RS(x/y) for y < > 0 

and x,y in S, 

IDIV 

D x D D union { TooSmall, TooBig } 

such that x DIVD y = RD(x/y) for 

y < > 0 and x,y in D but not x,y in S. 

IDIV requires two operands on top of the stack. The numeric value of the second item is 

algebraically divided by the numeric value of the top item. The fractional part of the 

floating point quotient is discarded and the integer part is left on top of the stack in 

canonical integer representation. 

 

 


Top-of-stack 

 


x: opnd(real) opnd(integer) 

 

 

6878 7530–007 5–21

Operator Set 

If the divisor (top of stack operand) equals zero, a Divide by Zero exception is generated; 

if the code stream is resumed, the result of the operator is a zero of the appropriate type 

(single or double precision). 

or 

IDIV: S x S I union { TooBig } 

such that x IDIV y = TI(x/y) for y < > 0 

and x,y in S, 

D x D Id union { TooBig } 

such that x IDIV y = TId(x/y) 

for y < > 0 and x,y in D but not x,y in S. 

If an Integer Overflow exception occurs and the code stream is resumed, the result of 

the operator is an integer representation of appropriate type (single or double precision) 

and the value is the maximum integer of appropriate type and sign. 

RDIV 

RDIV requires two operands on top of the stack. The numeric value of the second item is 

divided by the numeric value of the top item. The integer quotient with remainder is 

generated and only the remainder is left on top of the stack. The sign of the result is the 

same as the sign of the second item (the dividend). 

If the divisor (top of stack operand) equals zero, a Divide by Zero exception is generated; 

if the code stream is resumed, the result of the operator is a zero of the appropriate type 

(single or double precision). 

or 

RDIV: S x S S union { TooBig } 

such that x RDIV y = x - (TI(x/y) * y) 

for y < > 0 and x,y in S, 


such that x RDIV y = x - (TId(x/y) * y) 

for y < > 0 and x,y in D but not x,y in S. 

If both x and y are single_integers, then the result is a single_integer. 


the operator is of appropriate type (single or double precision) and the value is zero. 

NORM 

NORM requires an operand on the top of the stack. If the operand is single precision, it 

is converted to normalized single precision representation. If the operand is double 

precision, it is converted to normalized double precision representation. 

or 

NORM: S S union { TooSmall } 

such that NORM x = NS(x) for x in S, 

D D union { TooSmall } 

such that NORM x = ND(x) for x in D. 

5–22 6878 7530–007

AMIN and AMAX 

Operator Set 

AMIN and AMAX require two operands on top of the stack. The numeric values of the 

two operands are compared and the arithmetically lesser (or greater) of the two operand 

values is left as the result on top of the stack. If one of the input operands is single 

precision and the other input operand is double precision, the single precision operand is 

extended before the comparison and a double precision result is generated. If both of 

the inputs are single_integers, then so is the result. 

AMIN: S x S S (x,y in S) or 

D x D D (x,y in D but not x,y in S) such that 

 

x if x = y 

 

AMAX: S x S S (x,y in S) or 

D x D D (x,y in D but not x,y in S) such that 

 

y if x = y 

 

Numeric Relational Operators 

These six dyadic operators algebraically compare two real arguments to generate a 

Boolean result: 

EQUL 

NEQL 

LESS 

LSEQ 

GRTR 

GREQ 

 

Top-of-stack y: opnd(real) 

 

transformation: x: opnd(real) sp(Boolean) 

 

The operators are defined for x,y in S union D. The result is True or False, expressing the 

truth of the proposition x : y, where : represents the relation expressed in the operator 

name. 

6878 7530–007 5–23

Operator Set 

Range Test Operator 

Range Test computes the result of a double arithmetic inequality, L

Operator Set 

If RaI(x) equals TooBig, an Integer Overflow exception occurs. If the code stream is 

resumed, the result of the operator is a single_integer and the value is 8**13-1 with 

appropriate sign. 

If the argument is a nonzero single_integer, the result is the unmodified argument, 

therefore, bits [47:3] are preserved. For any other argument value, none of those three 

bits is set in the result if the corresponding bit is zero in the argument. 

NTIA 

NTIA requires an operand on top of the stack. The operand is converted to single_integer 

representation and the result is left on top of the stack. The top-of-stack transformation 

is the same as for NTGR. 

or 

NTIA: S I union { TooBig } 

D I union { TooBig } 

such that NTIA x = TI(x) for x in S or D 


the operator is a single_integer and the value is 8**13-1 with the appropriate sign. 

SNGL 

SNGL requires an operand on top of the stack. The operand is converted to normalized 

single precision representation and is left on top of the stack. 

 

Top-of-stack 

x: opnd(real) sp(real) 


 

SNGL: S Sn union { TooSmall } 

such that SNGL x = NS(x) for x in S, 

or 

D Sn union { TooSmall, TooBig } 

such that SNGL x = NS(RS(ND(x))) for x in D. 

SNGT 

SNGT requires an operand or copy WordDD on top of stack. An IndexedDD must have 

reindex enabled. 

If the argument is an operand, it is converted to normalized single precision 

representation and left on top of the stack. The top-of-stack transformation is the same 

as for SNGL. 

or 

SNGT: S Sn union { TooSmall } 

such that SNGT x = NS(x) for x in S, 

D Sn union { TooSmall, TooBig } 

such that SNGT x = NS(TS(ND(x))) for x in D. 

6878 7530–007 5–25

Operator Set 

If the argument is SingleDD, it is left on the stack unchanged. If the argument is a 

DoubleDD, it is left on the stack as a SingleDD and the element_size is set to single 

precision. 

 

Top-of-stack 

TOS: WordDD TOS’: SingleDD 


 

SNGT applied to a WordDD is equivalent to SESW applied to the same argument; this 

use of SNGT is obsolete. 

NTGD 

NTGD requires an operand on top of the stack. The operand is converted with rounding 

to double_integer representation and the result is left on the top of the stack. 

 

Top-of-stack 

x: opnd(real) dp(integer) 


 

NTGD: S Id union { TooBig } 

such that NTGD x = RId(XTND(x)) for x in S, 

or 

D Id union { TooBig } 

such that NTGD x = RId(x) for x in D. 

If the Integer Overflow exception occurs and code stream is resumed, the result of the 

operator is a double_integer and the value is 8**26-1 with appropriate sign. 

NTTD 

NTTD requires an operand on top of stack. The operand is converted with truncation to 

double_integer representation and the result is left on top of the stack. The top-of-stack 

transformation is the same as for NTGD. 

or 

NTTD: S Id union { TooBig } 

such that NTTD x = TId(XTND(x)) for x in S, 

D Id union { TooBig } 

such that NTTD x = TId(x) for x in D. 

If the Integer Overflow exception occurs and code stream is resumed, the result of the 

operator is a double_integer; the value is 8**26-1 with appropriate sign. 

5–26 6878 7530–007

Binary-to-Decimal Conversion 

Operator Set 

The binary-to-decimal conversion operators are variations of the scale right final 

operators; the result is a decimal digit sequence representing the remainder of the 

division by a power of ten. There are two operators: a static form (BCD) with the number 

of digits specified as a code parameter and a dynamic form (DBCD) with the number of 

digits supplied as a stack argument. 

The number to be converted is a stack argument that must be an operand; if necessary, 

that argument is integerized with the RId function. This integerized argument is referred 

to in the next examples as B (the binary integer). If Integer Overflow exception occurs 

because RId equals TooBig and then the code stream is resumed, the result of the 

operation is single or double precision according to the value of N (as specified in the 

next paragraph) and the value is all nines. 

|B| mod 10**N is converted to a sequence of N digits (each in the range {hex 0 to hex 

9}), where N is provided as a code parameter or a stack argument. N must be in the 

range {0 to 24}. The result is left-justified in an operand, which is single precision if N is 

12 or less and double precision if N is in the range {13 to 24}. The contents of the 

operand beyond the N-digit sequence are undefined. 

EXTF is set to: false (positive) if B >= 0, 

true (negative) if B < 0 and |B| mod 10**N > 0, 

undefined state if B < 0 and |B| mod 10**N = 0. 

OFFF is set to: true (overflow) if |B| >= 10**N, 

unchanged if |B| < 10**N. 

BCD 

The B operand is the only stack argument; N is a code parameter: 

 

Operator 

BCD N 

format: 

 

 

Top-of-stack 

B: opnd(real) opnd(BCD) 


 

DBCD 

Two operand stack arguments are required: 

 

 

N: opnd(integer) 

Top-of-stack 

 


B: opnd(real) opnd(BCD) 

 

 

6878 7530–007 5–27

Operator Set 

The topmost argument is integerized with the RaI rounding function, if necessary, to 

produce N. The second argument provides B. 

Mathematical Function Operator 

RSQR 

RSQR produces single precision approximations if the input is single and produces 

double precision approximations if the input is double. 

The argument must be an operand that is greater than or equal to zero. 

RSQR: { s : s in S and s >= 0 } S 

such that RSQR x in AS1(square root(x)) 

or 

{ d : d in D and d >= 0 } D 

such that RSQR x in AD1(square root(x)) 

The result of RSQR is greater than or equal to zero. 

Integer Representation Conversion Operators 

The two operators in this group perform conversions between signed-magnitude and 32bit 

two’s complement representations of single precision integers over a limited range of 

values. The range of result values (interpreted in the respective result representation) for 

both operators is: 

-(2**31) to 2**31-1 

Both the input stack argument and the result are single precision integers: 

 

Top-of-stack 

x: sp(integer) sp integer 


 

The canonical representation for a 32-bit two’s complement integer is a single precision 

operand with the high order 16 bits ([47:16]) set to zero. Bit 31 is treated as the sign. If 

that bit is false (zero), the remaining 31 bits directly represent the value as a positive 

integer. If bit 31 is true (one), the value is a negative integer whose magnitude is 

obtained by subtracting the value from 2**32. 

The argument for either operator must be a single precision integer operand in 

single_integer representation; no integerization will be performed. For input argument 

values within the valid range of results, the result value will remain the same, converted 

to the other representation. For both operators, bits [47:1] and [45:14] of the result will 

be zero. 

5–28 6878 7530–007

CVS2 

Operator Set 

The input argument is a signed single precision E-Mode integer operand. Bits [38:7] of 

the input are ignored and have no effect on the result. 

If the input is positive or the low order 32 bits of the argument are zero, the result is the 

low order 32 bits of the argument. Note that the two’s complement interpretation of the 

result will be negative if the result, taken as a 32 bit binary number, is greater than 

2**31-1. 

If the input argument is negative (any magnitude with low order 32 bits of zero is treated 

as positive, regardless of sign), the result is the 32-bit integer calculated by subtracting 

the low order 32 bits of the argument magnitude from 2**32. Note that the two’s 

complement interpretation of the result will be positive if the result, taken as a 32 bit 

binary number, is less than 2**31 

Bit 46 of the result will be zero. 

CV2S 

The input argument is a single precision E-Mode 32-bit integer. 

If the input value (as truncated) is positive (bit 31 false), the result is the positive E-Mode 

integer with that value, which will be less than 2**31. 

If the input value is negative (bit 31 true), the result is a negative E-Mode integer with 

the magnitude calculated by subtracting the input value from 2**32. 

Bit Vector Interpretation 

This group of operators provides various functions. Those operators that act on stack 

items either interpret the items as bit vectors or deal with the word as whole. In general, 

there are few restrictions on the type of stack items that are acted upon. 

Logical Operators 

Logical operators require one or two top-of-stack items. Either item may be of any type. 

The items are interpreted as 48-bit vectors, unless one or both are double precision 

items. In that case, they are interpreted as 96-bit vectors and if only one of the two 

items is double precision, the other is extended with 48 zero bits (whether that item is 

an operand or not). 

The logical operation is applied in parallel to each bit of the vectors and the result is left 

on top of the stack. For the monadic LNOT operator, the tag and extension of the result 

is the same as the tag and extension of the top of stack item. For the dyadic logical 

operators, the result is double precision if either argument is double precision; 

otherwise, the tag and extension of the result is the tag and extension of the second 

from top item. 

6878 7530–007 5–29

Operator Set 

The four logical operations are illustrated here in binary notation: 

NOT 01 = 10 

0011 AND 0101 = 0001 

0011 OR 0101 = 0111 

0011 EQV 0101 = 1001 

The dyadic logical operators effect the following transition: 

 

 

any(bit-vector) 

Top-of-stack 

 


any(bit-vector) any(bit-vector) 

 

 

LAND 

LAND requires two top-of-stack items. The logical AND of the two bit vectors is left on 

top of the stack. 

LOR 

LOR requires two top-of-stack items. The logical OR of the two bit vectors is left on top 

of the stack. 

LEQV 

LEQV requires two top-of-stack items. The logical EQV (equivalence) of the two bit 

vectors is left on top of the stack. 

LNOT 

LNOT requires a single top-of-stack item. All bits of the vector are complemented and its 

tag remains unchanged. 

 

Top-of-stack 

item: any(bit-vector) item’ 


 

Logical Relational Operator 

SAME 

SAME requires two top-of-stack items. The items are interpreted as 56- bit vectors 

(including tag and extension bits). If all corresponding bits of the two vectors have the 

same value, a True result is left on top of the stack; otherwise, a False result is left. If 

both items are double precision, the bit vector interpretation includes the second words. 

Note that if only one item is double precision, the result is necessarily false. 

5–30 6878 7530–007

any(bit-vector) 

Top-of-stack 

 


any(bit-vector) sp(Boolean) 

 

 

Literal Operators 

Literal operators place a single precision constant on top of the stack: 

 

Top-of-stack 

Null sp 


 

ZERO 

Operator Set 

ZERO leaves on top of the stack a single precision word with all bits initialized to zero. 

ONE 

ONE leaves on top of the stack a 1-bit integer equal to one. 

LT8 

LT8 leaves on top of the stack an 8-bit integer that is a copy of its one-syllable 

parameter. 

 

Operator 

LT8 Constant 

format: 

 

LT16 

LT16 leaves on top of the stack a 16-bit integer that is a copy of its two-syllable 

parameter. 

 

Operator 

LT16 Constant 

format: 

 

LT48 

LT48 leaves on top of the stack a single precision operand that is a copy of its six-syllable 

parameter. The parameter is taken from the first code word following the LT48 op code. 

6878 7530–007 5–31

Operator Set 

Padding syllables, if any, from the op code to the end of the word containing the op code 

are ignored. 

 

Operator ignored 

LT48 Constant 

format: if any 

 

word aligned 

Bit Vector Type Transfer Operators 

Operators in this group perform the following operations on the top-of-stack items. 

STAG Set the tag to an arbitrary value from the top of stack. 

XTND Append a low-order word of zeros, if necessary, to form a double precision 

operand, or set the element_size of a wordDD to double precision. 

JOIN Join two operands to form one double precision operand. 

SPLT Split an operand into two single precision operands. 

STAG 

STAG requires a tag value and an object item on top of the stack and leaves as its result 

an item whose tag is the tag value and whose 48 bits and 4-bit extension are copied 

from the object item. 

 

 

tag: sp opnd 

Top-of-stack 

 


object: any object’ 

 

 

The topmost argument must be a single precision operand. The tag value is extracted 

from field [3:4]; the remainder of the operand is ignored. 

The tag value must not be 2. 

The STAG operator is partially restricted; in user code, the only valid tag values are 4, 5, 

and 6. 

XTND 

XTND requires an operand or a copy WordDD on top of the stack. An IndexedDD must 

have reindex enabled. 

If the argument is a double precision operand, it is left on the stack unchanged. If it is 

single precision operand, it is converted to double precision representation by appending 

a second word whose fields are initialized to zero; the double precision result is left on 

the stack. Note that its numeric value is not changed. 

5–32 6878 7530–007

Top-of-stack 

TOS: opnd TOS’: dp 


 

Operator Set 

If the argument is a DoubleDD, it is left on the stack unchanged. If the argument is a 

SingleDD, it is left on the stack as a DoubleDD and its element_size is set to double 

precision. 

 

Top-of-stack 

TOS: WordDD TOS’: DoubleDD 


 

XTND applied to a WordDD is equivalent to SEDW applied to the same argument; this 

use of XTND is obsolete. 

JOIN 

JOIN requires two operands on top of the stack. A double precision item is constructed 

from the two operands and the result is left on top of the stack. 

The first and second words of the double precision result are taken from the first words 

of the second and top operands, respectively. The following possibilities arise from 

combinations of single and double precision operands: 

 

 

1) sp(w1) 3) dp(w1,w2) 

 

 

 

sp(w2) dp(w2,w1) sp(w3) dp(w3,w1) 

 

 

 

 

2) sp(w1) 4) dp(w1,w2) 

 

 

 

dp(w2,w3) dp(w2,w1) dp(w3,w4) dp(w3,w1) 

 

 

6878 7530–007 5–33

Operator Set 

SPLT 

SPLT requires an operand on top of the stack. Two single precision items are 

constructed from the operand and left on top of the stack. 

If the operand is single precision, it is left on the stack and a single precision zero is 

pushed on the stack above it. If the operand is double precision, its two words are 

converted to two single precision items. The first word is pushed on the stack first and 

the second word is left on the top of the stack. 

 

 

1) sp(0) 2) sp(w2) 

 

 

 

sp(w1) sp(w1) dp(w1,w2) sp(w1) 

 

 

Evaluate Word Structure Operators 

All operators in this group ignore the argument’s extension. 

RTAG 

RTAG requires one item on top of the stack; its result is a single_integer whose value is 

the tag of the item. 

 

Top-of-stack 

any sp(integer) 


 

CBON 

CBON requires an operand on top of the stack. The number of bits in the operand that 

have the value one are counted. If the operand is double precision, all 96 bits are 

examined. CBON leaves on top of the stack a 7-bit integer whose value is the ones 

count. 

 

Top-of-stack 

opnd(bit-vector) sp(integer) 


 

5–34 6878 7530–007

LOG2 

Operator Set 

LOG2 requires one item on top of the stack and leaves in its place a 6- bit integer that 

indicates the leading bit in the item having the value one. If all bits in the item are zero, 

LOG2 leaves an integer zero; otherwise, the integer value is the bit number plus one of 

the highest-order one bit. Only the first word of a double precision item is examined. 

 

Top-of-stack 

any(bit-vector) sp(integer) 


 

Word Manipulation Operators 

Word manipulation operators provide the capability to alter any partial field (excluding tag 

and extension) of a word in the stack called the destination; in some cases this is based 

on a field of another word in the stack called the source. The source can be an argument 

or an implicit bit value; the destination can be an argument or an implicit word of zeros. 

The altered destination item is left on the top of the stack. The following operations are 

provided: 

BSET, DBST Set a single destination bit 

BRST, DBRS Reset a single destination bit 

ISOL, DISO Create a destination whose low-order field is set from a field of the 

source 

INSR, DINS Set a field of the destination from the low-order field of the source 

FLTR, DFTR Set a field of the destination from a field of the source 

CHSN Complement the sign bit (bit 46) of the destination 

Source items may be of any type. Destination type is restricted only for CHSN, which 

requires an operand. 

If the source is a double precision item, the field is taken from its first word and the 

second word is discarded. If the destination is a double precision item, the bit or field 

altered is in its first word and the second word is retained unchanged in the double 

precision result. The following terms are used for bit/field specifications: 

Db The destination bit to be set or reset or be the high-order bit of the 

destination field 

Sb The high-order bit of the source field 

Len The length of both the source and destination fields 

There are static and dynamic operators corresponding to several of the operations. The 

static operators take Db, Sb, and Len specifications, as required, from the code 

parameters; the dynamic operators take them from stack arguments. 

Dynamic Db, Sb, and Len arguments must be operands; they are integerized with 

rounding (RaI function) if necessary. All Db and Sb values must be in the range {0 to 47} 

and Len values must be in {0 to 48}. 

6878 7530–007 5–35

Operator Set 

The effect of word manipulation operators are shown as an assignment to a field of the 

destination word. The remainder of the destination word is not changed. Note that Len 

equals zero is a valid specification of a null field; in this case, the destination is not to be 

altered. 

BSET 

BRST 

BSET sets a single destination bit: destination.[Db:1] := 1. 

BRST resets a single destination bit: destination.[Db:1] := 0. 

The destination is the only required top of stack item and Db is specified by a parameter. 

 

Operator BSET 

Db 

format: BRST 

 

 

Top-of-stack 

dest: any(bit-vector) dest’ 


 

DBST 

DBRS 

DBST sets a single destination bit: destination.[Db:1] := 1. 

DBRS resets a single destination bit: destination.[Db:1] := 0. 

The required initial stack state includes Db. 

 

 

Db: opnd(integer) 

Top-of-stack 

 



 

 

5–36 6878 7530–007

ISOL 

Operator Set 

ISOL creates a single precision destination word initialized to zero and then sets its loworder 

field from a field of the source: destination := 0; destination.[Len-1:Len] := 

source.[Sb:Len]. The source is an argument; Sb and Len are specified by parameters: 

 

Operator 

ISOL Sb Len 

format: 

 

 

Top-of-stack 

source: any(bit-vector) sp 


 

DISO 

DISO creates a single precision destination word initialized to zero and then sets its 

low-order field from a field of the source: destination := 0; destination.[Len-1:Len] := 

source.[Sb:Len]. Sb and Len are arguments above the source. 

 

 

Len: opnd(integer) 

 

 

 

Sb: opnd(integer) 

Top-of-stack 

 


source: any(bit-vector) sp 

 

 

INSR 

INSR sets a field of the destination from the low-order field of the source: 

destination.[Db:Len] := source.[Len-1:Len]. The destination and source are arguments; 

Db and Len are specified by parameters: 

 

Operator 

INSR Db Len 

format: 

 

 

 

source: any(bit-vector) 

Top-of-stack 

 



 

 

6878 7530–007 5–37

Operator Set 

DINS 

DINS sets a field of the destination from the low-order field of the source: 

destination.[Db:Len] := source.[Len-1:Len]. Db and Len are arguments between the 

destination and source; note that the source is topmost: 

 

 


 

 

 


Top-of-stack 

 



 

 

 


 

 

FLTR 

FLTR sets a field of the destination from a field of the source: destination.[Db:Len] := 

source.[Sb:Len]. The destination and source are arguments; Db, Sb, and Len are 

specified by parameters: 

 

Operator 

FLTR Db Sb Len 

format: 

 

 

 


Top-of-stack 

 



 

 

FLTR is obsolete, superseded by ISOL INSR. 

5–38 6878 7530–007

DFTR 

Operator Set 

DFTR sets a field of the destination from a field of the source: destination.[Db:Len] := 

source.[Sb:Len]. Db, Sb, and Len are arguments above the destination and source: 

 

 


 

 

 

Sb: opnd(integer) 

Top-of-stack 

 



 

 

 


 

 

 


 

 

CHSN 

The CHSN operator requires an operand on top of the stack. CHSN complements a 

single destination bit: destination.[46:1] := NOT destination.[46:1]. 

 

Top-of-stack 

TOS: opnd TOS’ 


 

Linear Index-Function Operator 

OCRX 

OCRX computes a linear integer function of an integer index, with bounds checking. The 

function is defined as: 

RelativeIndex (offset, width, index) = offset + (index-1)*width; 

where index must be in the range {1 to limit}. 

OCRX leaves on top of the stack the result of the RelativeIndex function applied to 

values derived from two arguments: 

6878 7530–007 5–39

Operator Set 

 

 

sp(ICW) 

Top-of-stack 

 


index: opnd(integer) sp(integer) 

 

 

The Index Control word (ICW) must be a single precision operand. It contains three 

fields: 

ICW_width [47:16] = the width coefficient 

ICW_limit [31:16] = the upper bound for the index 

ICW_offset [15:16] = the offset coefficient 

The index argument must be an operand; it is integerized with rounding (RaI function) if 

necessary. 

If the index is not in the range {1 to ICW_limit}, an interrupt is generated. Otherwise, 

ORCX leaves on top of the stack a single_integer whose value is RelativeIndex 

(ICW_offset, ICW_width, index). 

OCRX is obsolete, superseded by the obvious sequence of arithmetic operators and 

ASRT or AVER. 

5–40 6878 7530–007

Reference Generation and Evaluation Operators 

Operator Set 

The common feature of this operator group is the generation and evaluation of 

references and chains of reference. The group consists of reference generation 

operators (generators) and operators that evaluate references in order to read a target 

item onto the stack (read evaluators) or store an item from the stack into a target 

location (store evaluators). 

Basic evaluation of a reference consists of calculating the absolute address to which it 

refers. Read evaluation consists of fetching the contents of the referenced location; 

store evaluation consists of writing the contents of that location. 

Double Precision 

References to double precision operands refer to the first word. The need for a second 

word may be indicated by the tag of the first word or by the reference 

(IndexedDoubleDD). The second word is the virtual successor of the first; it may be in 

the next higher memory location or the two words may be the last word of one page and 

the first word of the next page in the same virtual segment. Such separation can occur 

only when access is via an IndexedDoubleDD with an odd index value. 

Stack References 

A stack is designated by its stack_number. Each stack is an actual segment whose 

ASD_number is its stack_number. 

Environment Link Evaluation 

The basic evaluation of an environment link consists of computing the absolute address 

of the base of the referenced AR by adding the displacement to the base address of the 

referenced stack or non-stack segment. 

Environment links occur in SIRWs and ENVWs. Those in SIRWs are evaluated as the 

SIRW is evaluated. Those in ENVWs are evaluated when the environmental chain is 

traversed to update display registers. 

Evaluation of References 

Read and store evaluators share the general capability to process a reference or chain of 

references in order to locate some target item. Initial references may be address couple 

parameters, SIRWs, IndexedDDs, sometimes ASRWs, and (for LODT) integers. 

Reference chains may contain SIRWs, IndexedDDs, and PCWs. 

Definition of valid target items and allowable reference chains depends on the function 

of the particular operator; evaluation of each element of a reference chain and of IRW 

chains is common to the operator group. The following paragraphs define evaluation of 

each reference form, IRW chain evaluation, and the notation used for each operator to 

specify allowable reference chains and valid target items. 

6878 7530–007 5–41

Operator Set 

Address Couple Evaluation 

Address couples occur in operator parameters in either fixed or variable fence forms. A 

name-call operator uses its address-couple parameter to construct an SIRW on the stack. 

Other operators use their address-couple parameter as their own initial reference. 

Basic evaluation of an address couple (lambda,delta) consists of calculating the address 

of the referenced word, by adding delta to the base address of the activation record 

whose lex level is specified by lambda. For lambda equal to LL, the base address is in 

D[LL]; for lambda less than LL, the activation record is located LL minus lambda steps 

down the environmental chain (its base address is captured in D[lambda]). 

In a valid address couple, lambda is less than or equal to LL and delta is less than the 

width of the referenced AR. For the topmost AR, the upper boundary includes only items 

that have been explicitly pushed, not items in the expression stack. The restrictions of 

this paragraph are incumbent upon the compilers for all ClearPath MCP. 

SIRW Evaluation 

Basic evaluation of an SIRW consists of calculating the address of the referenced word; 

SIRW.offset is added to the address derived from the Environment Link. (The ENTR 

operator uses the Environment Link address, as well as the sum.) 

No validity check is required on the magnitude of the offset value or the environment-link 

displacement value during SIRW evaluation. SIRWs are created from the address couple 

whose lambda is verified at that time. (If software constructs or modifies an SIRW, it is 

trusted to do so correctly.) 

IndexedDD Evaluation 

Basic evaluation of a data descriptor as a reference is possible only for an IndexedDD 

referring to a present segment. IndexedCharDDs are treated as IndexedSingleDDs, with 

any char_index value ignored. The evaluation consists of calculating the address of the 

referenced word. 

Access checking is performed upon evaluation of IndexedDDs. A store is aborted if write 

is disabled via the DD. 

In cases where the target of an IndexedDD is an operand, the element type of the 

operand is determined by the element_size field of the IndexedDD. The element_size 

value of single (including characters) or double precision overrides the tag of the target 

operand. All operators that evaluate IndexedDDs obey this convention except the Load 

Transparent, overwrite, and transfer words operators. 

An IndexedDD may be used to reference words of any type appropriate to the 

referencing operator. The exception is LOAD, which uses an IndexedDoubleDD only to 

reference an operand. 

5–42 6878 7530–007

PCW Evaluation 

Operator Set 

In the context of reference chain evaluation, evaluation of a PCW consists of an 

accidental procedure entry. The PCW is assumed to point to a function with no 

parameters, whose returned value is either the target of the chain or another valid 

reference. The net result of the accidental entry is that the place of the PCW in the 

reference chain is taken by the item returned by the function. 

The accidental entry is accomplished by the aACCE action. The function must terminate 

with a RETN (return) operator, leaving an item on top of the stack. 

Reference Chains 

Operators that evaluate reference chains start from an initial reference and apply 

successive reference read evaluation, according to a set of chaining rules until a target 

item is produced. For each of these operators, the set of initial references and targets is 

specified using the following notation: 

::= {set of reference items} 

::= {set of target items} 

Chaining rules are specified by indicating the valid evaluation results for each reference 

form that may be part of the chain. The form of such specification is: 

reference evaluation results 

where the arrow indicates read evaluation of the reference as defined in the preceding 

paragraphs. Evaluation results can include a reference, which is subsequently evaluated, 

or a target. 

Chaining rule notation is illustrated in this example: 

::= {SIRW, IndexedDD} 

::= {operand} 

SIRW SIRW 

IndexedDD 

PCW 

 

IndexedDD 

PCW SIRW 

IndexedDD 

The term IRW denotes a reference in {address couple, SIRW}. The term IRW chain 

denotes a reference chain whose initial reference is an address-couple parameter or 

SIRW and that otherwise contains only SIRWs; an SIRW chain contains only SIRWs, 

including the initial reference. 

6878 7530–007 5–43

Operator Set 

Evaluation of the chain continues until a target is encountered or an interrupt occurs. 

• Touch Reference (or Touch Load or Missing PCW) interrupt is generated if the target 

of any reference is an untouched DD. Upon resumption after the interrupt, evaluation 

continues; the incorrect object has presumably been replaced by another reference 

or a target. 

• Absent Segment interrupt is generated if a reference designates a nonpresent 

segment; evaluation continues when the code stream is resumed with the segment 

present. 

• If an item is encountered that is not a valid result and not one of the service requests 

previously noted, an error interrupt is generated. 

A reference chain must not loop, because the operator cannot complete. (The processor 

generates a Loop Timer alarm interrupt whenever an operator does not complete in a 

reasonable time.) 

Reference Generation Operators 

NAMC 

On Libra 6xx and 7xx systems, the NAMC operator transforms an address couple in the 

code stream into an SIRW. NAMC is a two-syllable operator with a special structure, a 2bit 

op code and a 14-bit variable-fence address couple: 

 

Operator : 

NAMC : address couple 

format: : 

 

: 

2 : 14 

The SIRW is constructed to point to the word in the stack referenced by the address 

couple (lambda,delta). The offset field is set from delta. The env_link field is set to 

designate the normal or pseudo activation record at lex level lambda in the current 

addressing environment. Since the display registers are maintained as (ASD_number, 

displacement) couples, the Environment Link value is in D[lambda]. 

 

Top-of-stack 

Null SIRW 


 

5–44 6878 7530–007

LNMC 

Operator Set 

LNMC is equivalent to NAMC, except that its parameter is a fixed-fence rather than a 

variable-fence address couple. LNMC is a four-syllable operator whose appearance in the 

code stream is: 

 

Operator : 

LNMC lam: delta 

format: : 

 

: 

4: 12 

NMC0 

NMC1 

NMC2 

NMC3 

NMC0, NMC1, NMC2, and NMC3 are equivalent to NAMC, except that lambda is 

specified directly by the operator code itself. They are three syllable operators whose 

appearance in the code stream is: 

 

Operator 

NMCx delta 

format: 

 

The delta portion of the address couple appears as a two-syllable parameter to the 

operator. 

STFF 

STFF performs no action on Epsilon systems. 

aAPIX 

This common action is defined as a procedure with two formal parameters, a descriptor 

DD, and an index value vI (a number of elements of the same size defined by the DD 

element_size). The action is to index DD by vI. The clients of aAPIX and their invocations 

are as follows: 

• The indexing operators pass DDs, both indexed and unindexed, paged and unpaged. 

• All array operators reindex indexed DDs via aAPIX. 

The aAPIX action constructs an IndexedDD whose virtual index is 

vX = vD + vI*df 

6878 7530–007 5–45

Operator Set 

where 

vX is the new virtual index. 

vD is the virtual index of the DD (0 for unindexed DD). 

vI is the argument to aAPIX. 

df is 2 if DD is double precision and 1 otherwise. 

For application to a DD, the vX must be represented in up to three components: page 

index (pX), word index (wX), and character index (cX); these components are defined as 

follows: 

unpaged (pX not relevant): 

single or double: wX = vX 

hex: cX = vX MOD 12; wX = vX DIV 12 

EBCDIC: cX = vX MOD 6; wX = vX DIV 6 

paged: (p represents 2**13) 

single or double: wX = vX MOD p; pX = vX DIV p 

hex: cX = vX MOD 12; wX = vX DIV 12 MOD p; pX = vX DIV 12 DIV p 

EBCDIC: cX = vX MOD 6; wX = vX DIV 6 MOD p; pX = vX DIV 6 DIV p 

When pX = n > 0, wX = 0, and (if applicable) cX = 0, the same element possibly could be 

designated with pX = n-1 and wX = 2**13. A descriptor could designate the last+1 

element of a page instead of the first element of the successor page. This alternative 

representation is not generated by Epsilon processors. 

The quotient pX is used to index the page table. For indexing a paged unindexed DD, the 

DD itself provides the reference to the page table. For reindexing an indexed DD that 

designates a page, a reference to the page table is extracted from the ASD designated 

by the DD. Each page ASD contains a reference to the original SingleDD for that page; 

this reference is an indexed copy of the pagetable DD. 

The new virtual index must be representable in an IndexedDD if the aAPIX client uses or 

returns the result; it is not necessary if the indexing operation is performed in a nonupdate 

Data Array operator in anticipation of an iteration that never occurs. The 

representable values have: 

vX >= 0 

pX < Pages (for paged DDs) 

wX < field limit 

where Pages = page-table length 

and field limit = 2**20 for WordDDs, 2**16 for CharDDs. 

Pages is defined as ASD.AS_length in the ASD for the page table. 

5–46 6878 7530–007

Operator Set 

Valid representations have wX less than or equal length in words of the designated 

actual segment. Equality is expressly permitted; update pointer operators can generate 

an IndexedDD to the first element beyond the array. However, INDX treats the equality 

as as an error. 

If the data segment is unpaged, an IndexedDD is constructed by making a proper copy 

of the DD, marking it indexed, and inserting the index. For a WordDD, an 

IndexedWordDD is constructed by setting the index field to wX with the field- width limit 

at 2**20-1. For a CharDD, an IndexedCharDD is constructed by setting the word_index 

field to wX and the char_index field to cX with the field-width limit on wX at 2**16-1. 

If the data segment is paged, an IndexedDD is constructed by making a proper copy of 

the page descriptor, which is located by indexing the page table by pX. The element_size 

field is copied from the indicated DD. An IndexedWordDD is constructed with wX in the 

index field or an IndexedCharDD is constructed by setting word_index to wX and 

char_index to cX; field overflow cannot occur. 

INDX 

INDX applies an integer index to a DD and leaves on top of the stack an IndexedDD 

pointing to the specified element. If the DD is a WordDD, the result is an 

IndexedWordDD and if it is a CharDD, the result is an IndexedCharDD. A copy DD may 

be on the stack initially; an original or copy DD may be addressed by an SIRW chain. 

::= {unindexed copy DD, 

IndexedDD, 

initial reference} 

::= SIRW 

::= {unindexed DD, 

IndexedDD } 

SIRW SIRW 

 

INDX requires the Descriptor Indication and an operand index value on top of the stack in 

either order. 

6878 7530–007 5–47

Operator Set 

 

 

Desc-Ind: SIRW, DD 

Top-of-stack 

 


index: opnd(integer) IndexedDD 

 

 

or 

 

 

index: opnd(integer) 

Top-of-stack 

 


Desc-Ind: SIRW, DD IndexedDD 

 

 

The index value must be an operand. The Descriptor Indication must be an SIRW or a 

copy WordDD or Char DD. In describing the indexing operation, the unqualified term DD 

is applied to the indicated descriptor, the one to which the index will be applied. If the 

Descriptor Indication is a data descriptor, it is the DD; if the Descriptor Indication is an 

SIRW, the DD is the target of the SIRW chain. 

The index value is integerized with rounding (RaI function) if necessary; its magnitude 

must not exceed MaxInx. The resulting value is called I within this description. 

The DD may be unindexed or indexed; an indexed DD must have reindex enabled. The 

new virtual index is the sum of the current virtual index of DD (which is 0 if DD is 

unindexed) plus I; the sum must be in the range {0 to N-1}, where N is the number of 

elements in the virtual segment referenced by DD. (This constraint can be taken as a 

summary of the detailed constraints defined in aAPIX.) 

The index value, I, is applied to the descriptor DD using the common action aAPIX; INDX 

aborts if the indexing operation does not produce a valid descriptor. 

There are two access rights in an IndexedDD: write enable and reindex enable. The 

indexing operation determines the access rights as follows: 

write Copied from indicated DD 

reindex Enabled 

The following service interrupts, which overlap those for reference chain evaluation, may 

be generated by INDX if the DD is exceptional: 

Absent Segment page table is absent 

DD designates an absent segment 

Touch Reference is untouched DD 

page DD is untouched DD 

5–48 6878 7530–007

MPCW 

Operator Set 

MPCW is a literal operator that constructs a PCW at the top of the stack from a sixsyllable 

parameter in the code stream. The parameter is taken from the first code word 

following the MPCW op code. Padding syllables, if any, from the op code to the end of 

the word containing the op code are ignored. 

 

 

Operator ignored 

MPCW PCW skeleton 

format: if any 

 

 

word aligned 

 

Top-of-stack 

Null PCW 


 

The valid ranges for PCW-skeleton values in user programs are: 

skeleton_psi: 0 to 5 

skeleton_pwi: 0 to length-1 of the code segment 

skeleton_CS: 0 

skeleton_LL: sdll+1 to LL+1 

sdll: 0 or 1 

sdi: 1 to length-1 of activation record at level sdll 

The fields skeleton_psi, skeleton_pwi, skeleton_CS, and skeleton_LL are copied, 

respectively, from the skeleton into corresponding fields psi, pwi, CS, and lex_level of 

the PCW. The address couple (sdi,sdll) is evaluated to fetch a CSD; the ASD_ref field of 

the CSD is copied into the PCW. All other PCW fields are set to zero. The PCW tag is set 

to 7. A Touch CSD service interrupt is generated if the CSD is untouched. 

MPWx 

These two operators create a PCW from a reference to a Code Segment Descriptor and 

a code index. 

MPWL 

MPWP 

 

 

Desc-Ind: SIRW, IDD 

Top-of-stack 

 


index: SP(integer) PCW 

 

 

6878 7530–007 5–49

Operator Set 

The descriptor indication must be an SIRW or an IndexedDD pointing directly to a Code 

Segment Descriptor. The char_index in an IndexedCharDD will be ignored. The integer 

code index must be a 16-bit integer whose most significant 13 bits become pwi, while 

the least significant 3 bits (value less than 6) become psi. 

The operators use the index to produce a PCW from the Code Segment Descriptor. The 

ASD_ref is set from the CSD. The pwi and psi is formed from the code index argument. 

Lex_level is determined by the operator: MPWL sets lex_level to LL, MPWP sets 

lex_level to LL+l. The control_state value is set to zero. 

Reference Modification Operators 

SEsz 

These four operators set the element size of a copy DD: 

SESW 

 

Top-of-stack 

TOS: DD TOS’: SingleDD 


 

SEDW 

 

Top-of-stack 

TOS: DD TOS’: DoubleDD 


 

SE4C 

 

Top-of-stack 

TOS: DD TOS’: hex CharDD 


 

SE8C 

 

Top-of-stack 

TOS: DD TOS’: EBCDIC CharDD 


 

The argument must be an indexed or unindexed copy WordDD or CharDD; an 

IndexedDD must have reindex enabled. The result is the same DD with its element size 

set to a value implied by the operator name: single, double, hex, or EBCDIC for SESW, 

SEDW, SE4C, or SE8C, respectively. The index field of the DD is not modified. 

5–50 6878 7530–007

Operator Set 

If the argument is an IndexedWordDD, SE4C and SE8C require that the index value be 

less than 2**16. If the argument is an IndexedCharDD, SESW and SEDW ignore the 

char_index value, setting that field to zero in the result, while SE4C and SE8C leave it 

unmodified. It is an error for SE4C or SE8C to be applied to an IndexedCharDD with a 

different element size and a non-zero char_index. 

NOWR 

The NOWR operator disables the write access right in references. The operator requires 

one argument, which must be a copy DD. The result is the argument with write access 

disabled. 

 

Top-of-stack 

TOS: DD TOS’ 


 

NORX 

The NORX operator disables reindexing in indexed DDs. The operator requires one 

argument, which must be an indexed DD. The result is the argument with reindex 

disabled. 

 

Top-of-stack 

TOS: IndexedDD TOS’ 


 

Descriptor Attribute Extraction Operators 

The descriptor attribute extraction operators are provided to extract the value of certain 

attributes of DDs. In each case, a copy DD is consumed as the argument and a 

single_integer is left as the result. 

GLEN 

The argument must be a copy WordDD or CharDD; the result is the declared length of 

the designated segment, reported in the element_size of the DD. 

 

Top-of-stack 

copy DD sp(integer) 


 

The declared length is computed from three values in the ASD referenced by the DD: 

W = AS_length: words in the designated actual segment 

D = deficit: words not counted in the declared length 

N = nybbles: 4-bit characters reported in the declared length 

6878 7530–007 5–51

Operator Set 

Define S = W for unpaged DDs and S = W * 2**13 for paged DDs. Then the declared 

length L is defined for each element size as: 

single: L = S-D 

double: L = (S-D) DIV 2 

EBCDIC: L = (S-D)*6 + N DIV 2 

hex: L = (S-D)*12 + N 

GINX 

The GINX operator requires a copy WordDD or CharDD as its argument. For an 

indexedDD, the result is the virtual index of the DD; for an unindexed DD, the result is 

zero. Note that for an IndexedDoubleDD, the virtual index is in single words. 

 

Top-of-stack 



 

GESZ 

The GESZ operator requires a copy DD as its argument. The result is the element_size 

encoding of the DD, as a 3-bit integer; the result is 0, 1, 2, or 4 for a SingleDD, 

DoubleDD, hex CharDD, or EBCDIC CharDD, respectively and it is in {3, 5, 6, 7} if the DD 

had one of those invalid encodings. (GESZ is functionally equivalent to ISOL 42:3 on a 

copy DD.) 

 

Top-of-stack 



 

Read Evaluation Operators 

aFOP 

The common action aFOP is defined to fetch a single or double precision operand via an 

IRW an IndexedWordDD, or an IndexedCharDD (which is treated like an 

IndexedSingleDD, with any char_index ignored). The action can be described as a 

procedure with one formal parameter, the reference to be evaluated, and four possible 

results: 

• An operand value 

• A non-operand value (via an IRW, or via IndexedSingleDD or IndexedCharDD for 

LOAD) 

• A service interrupt 

• An error interrupt 

5–52 6878 7530–007

Operator Set 

For most clients, aFOP generates an error interrupt if the referenced word does not have 

a tag in {0,2}. The exceptions are value-call and LOAD, for which a non-operand may be a 

chained reference or a target, respectively. If the reference is an address couple or 

SIRW, or the reference is an IndexedSingleDD or IndexedCharDD and the client is 

LOAD, the non-operand value is returned to the client operator. 

If the reference is an IRW and the referenced word has a tag of 0 or the reference is an 

IndexedSingleDD or IndexedCharDD and the referenced word has a tag in {0,2}, the 

referenced word is fetched and the tag set to zero (if necessary) to form an operand 

value. The extension is not modified. 

If the reference is an IRW and the fetched word has a tag of 2, its successor word (at 

the next higher memory address) is fetched. That word must have a tag in {0, 2}; the 

referenced word and its successor are joined as the first and second words of a double 

precision operand (with tag 2) to form an operand value. 

If the reference is an IndexedDoubleDD, the referenced word and its successor are 

fetched; each must have a tag in {0,2}. The two words are joined as the first and second 

words of a double precision operand (with tag 2) to form an operand value. A split across 

a page boundary can occur if an IndexedDoubleDD is so constructed that its index refers 

to the last word of a page. 

VALC 

The VALC operator evaluates a reference chain whose beginning is an address-couple 

parameter; the target must be an operand, which is left on top of the stack. VALC is a 

two-syllable operator with a special structure, a 2-bit op code and a 14-bit variable-fence 

address couple: 

 

Operator : 

VALC : address couple 

format: : 

 

2 : 14 

 

Top-of-stack 

Null opnd 


 

6878 7530–007 5–53

Operator Set 

Reference chain evaluation performed by VALC is: 

::= {address couple} 

::= {operand} 

address couple SIRW 

IndexedDD 

PCW 

 

SIRW SIRW 

IndexedDD 

PCW 

 

IndexedDD 

PCW SIRW 

IndexedDD 

 

Reference evaluation is performed by invocation of the common action aFOP. An 

operand value is left on the stack as the result of VALC and any non- operand value is 

examined as an element of the reference chain. If a PCW must be evaluated, accidental 

entry is performed by invoking the common action aACCE. Return from the function 

causes VALC to be resumed in restart mode; the operator ignores its code parameter 

and consumes a stack argument as the target of the PCW. 

LVLC 

LVLC is equivalent to VALC, except the parameter is a fixed-fence rather than a variablefence 

address couple. LVLC is a four-syllable operator whose appearance in the code 

stream is as follows: 

 

Operator : 

LVLC lam : delta 

format: : 

 

: 

4 : 12 

VLC0 

VLC1 

VLC2 

VLC3 

VLC0, VLC1, VLC2, and VLC3 are equivalent to VALC, except that lambda is specified 

directly by the operator code itself. They are three syllable operators whose appearance 

in the code stream is: 

 

Operator 

VLCx delta 

format: 

 

5–54 6878 7530–007

The delta portion of the address couple appears as a 2 syllable parameter to the 

operator. 

NXLV 

Operator Set 

NXLV performs an INDX (index) operation to produce an IndexedDD and then evaluates 

the IndexedDD to fetch an operand. The required initial stack state is the same as that 

for INDX. 

 

 


Top-of-stack 

 


index: opnd(integer) opnd 

 

 

or 

 

 


Top-of-stack 

 


Desc-Ind: SIRW, DD opnd 

 

 

::= {copy unindexed DD, 

IndexedDD, 


::= SIRW 


IndexedDD } 

SIRW SIRW 

 

If theDD is successfully indexed, the ultimate target is fetched by read evaluation of the 

IndexedDD: 

IndexedDD operand 

The IndexedDD is evaluated by invoking the common action aFOP; an operand value is 

left on the stack as the result of NXLV. 

6878 7530–007 5–55

Operator Set 

NXLN 

NXLN performs an INDX (index) operation to produce an IndexedDD and then evaluates 

the IndexedDD to fetch an unindexed DD; a copy of that DD is left on top of the stack. 

The required initial stack state is the same as that for INDX. 

 

 


Top-of-stack 

 


index: opnd(integer) unindexed copy DD 

 

 

or 

 

 


Top-of-stack 

 


Desc-Ind: SIRW, DD unindexed copy DD 

 

 

::= {unindexed copy DD, 

IndexedDD, 


::= SIRW 


IndexedDD } 

SIRW SIRW 

 

If the DD is successfully indexed, the ultimate target is fetched by read evaluation of the 

IndexedDD, treating the IndexedDD as a SingleDD (char_index is ignored for an 

IndexedCharDD): 

IndexedDD unindexed DD 

The target is fetched as a copy and left on the top of the stack. A service interrupt 

(Touch Load) is generated if the target of the IndexedDD is untouched. 

5–56 6878 7530–007

EVAL 

Operator Set 

The purpose of EVAL is to evaluate a reference chain in order to locate some target and 

then leave on top of the stack the reference whose evaluation produced the target. 

 

Top-of-stack 

ref: SIRW, IDD SIRW, IDD 


 

Reference chain evaluation performed by EVAL is: 


::= not {SIRW, IndexedDD, PCW} 

SIRW SIRW 

IndexedDD 

PCW 

 

IndexedDD * no evaluation -- see below * 

PCW SIRW 

IndexedDD 

If a target is located, the reference whose evaluation produced the target is left on top of 

the stack as the result. If an IndexedDD is encountered, it is left as the result without 

being evaluated. In effect, an IndexedDD is treated as if it had been evaluated and a 

target had been the result. 

If a PCW must be evaluated, accidental entry is performed by invoking the common 

action aACCE. EVAL deletes the Initial Reference and then invokes aACCE, so that the 

result of the accidental-entry procedure becomes the new Initial Reference. 

Almost every data type is specified as either a valid reference or a target for EVAL. A 

stack-linkage word is not a proper target, but the processor cannot enforce this rule. 

6878 7530–007 5–57

Operator Set 

LOAD 

LOAD performs a single evaluation of the Initial Reference and if the result is a target, it 

is left on top of the stack. 

 

Top-of-stack 

ref: SIRW, IDD SIRW, copy DD, Data Word 


 

::= {SIRW, IndexedWordDD,IndexCharDD} 

::= {operand, tag-4 word, tag-6 word, 

SIRW, any data descriptor} 

SIRW 

IndexedSingleDD 

IndexedCharDD 

IndexedDoubleDD operand (target) 

Reference evaluation is performed by invocation of the common action aFOP. An 

operand value or other valid target is left on the stack as the result of LOAD. If the target 

is an original DD, it is fetched as a proper copy. A service interrupt (Touch Load) is 

generated if the target is an untouched DD. 

LODT 

LODT performs a single evaluation of the Initial Reference and leaves the result on top of 

the stack with no restriction placed on the type of the result: 

 

Top-of-stack 

ref: SIRW, IDD, ASRW, integer address any 


 

::= {SIRW, IndexedDD, 

integer address (restricted), 

ASRW (restricted) } 

::= {any word} 

SIRW 

IndexedDD 

ASRW 

Integer 

The applicability of the LODT in user programs is partially restricted; the reference 

argument is never an operand or ASRW and the target is never a touched original DD. 

5–58 6878 7530–007

Operator Set 

If the Initial Reference is an SIRW, IndexedDD, or ASRW, it is evaluated normally; a 

single-word fetch is performed regardless of the element_size of an IndexedDD (an 

IndexedCharDD's char_index is ignored). An integer Initial Reference is interpreted as an 

absolute address from which the target is fetched. 

The addressed target word is left on top of the stack. If its tag is 2, the second word of 

the item left on top of the stack is zero. (Apart from the handling of tag=2, the LODT 

operator does not examine or alter the target word in any way.) 

Normal Store Operators 

aSOP 

The common action aSOP is defined to store a single or double precision operand value 

via an IRW, an IndexedWordDD, or an IndexedCharDD (which is treated like an 

IndexedSingleDD, with any char_index ignored). The action can be described as a 

procedure with two formal parameters, the reference to be evaluated and the object 

stored. An IndexedDD must be write-enabled. 

The type of store object must match that of the target location; one of the following 

statements must be true: 

The operand is single precision and: 

the final reference is an IndexedSingleDD or IndexedCharDD 

the final reference is an IRW and the target is in {single datum}. 

The operand is double precision and: 

the final reference is an IndexedDoubleDD or 

the final reference is an IRW and the target is in {double datum}. 

The set (single datum) is defined as the type union: 

{tag-0 word (single precision operand), 

tag-4 word, 

tag-6 word (uninitialized single datum) }. 

The set {double datum} is defined as the type union: 

{tag-2 word (double precision operand) }. 

If the operand is single precision, it is stored at the target location. 

If the operand is double precision, the first word is stored at the target location and the 

second at the successor of the target. The successor word must contain a Data Word. A 

split across a page boundary occurs if the final reference is an IndexedDoubleDD so 

constructed that its index refers to the last word of a page. 

Single precision operands are always stored with tag = 0 and both halves of a double 

precision operand are stored with tag = 2. Note that the target type can be changed by a 

normal store operation; an uninitialized datum can be changed to an operand and a single 

or double precision operand can be changed to the other if store is via an IndexedDD. 

6878 7530–007 5–59

Operator Set 

If an error interrupt is generated while the second half of a double precision value is 

being stored, the first half of the item has not been stored. 

STOD 

STON 

Normal store operators evaluate a reference chain in order to store an operand from the 

stack (the store object) into a target location. Reference chain evaluation performed by 

store operators is: 


::= Data Word 

SIRW SIRW 

IndexedDD 

PCW 

 

IndexedDD 

PCW SIRW 

IndexedDD 

For STOD and STON, the Initial Reference and the operand are required on top of the 

stack, in either order. (For best performance, address couple cases should emit NAMC 

STO-.) STOD deletes both the Initial Reference and the operand from the stack: 

 

 

ref: SIRW, IDD 

Top-of-stack 

 


object: operand Null 

 

 

or 

 

 

object: operand 

Top-of-stack 

 


ref: SIRW, IDD Null 

 

 

5–60 6878 7530–007

Operator Set 

STON deletes the Initial Reference but leaves the operand unchanged on top of the 

stack: 

 

 

ref: SIRW, IDD 

Top-of-stack 

 


object: operand object 

 

 

or 

 

 

object: operand 

Top-of-stack 

 


ref: SIRW, IDD object 

 

 

The operator performs read evaluation of the reference chain followed by store 

evaluation of the final reference to the target. If a PCW must be evaluated, accidental 

entry is performed by invoking the common action aACCE, so that the result of the 

accidental entry procedure becomes a new Initial Reference. 

The operand is stored at the final target location by invocation of the aSOP common 

action. 

Overwrite Operators 

Overwrite operators perform a single evaluation of the Initial Reference and store some 

item from the stack (the store object) into the resultant target location. The arrow 

indicates store evaluation for these operators, although under some circumstances, the 

processor may also read the target contents. 

::= {SIRW, IndexedDD, 

ASRW (restricted) } 

::= any item 

SIRW 

IndexedDD 

ASRW 

The topmost stack item must be an Initial Reference; the second stack item is the Store 

object. The store object may be of any type. 

A write evaluation of the initial reference is performed; write access is required. 

6878 7530–007 5–61

Operator Set 

The applicability of overwrite operators in user programs is partially restricted; the ASRW 

form of reference is not used, the store object is typically a reference, operand, or tag-4 

or tag-6 word and the store target is not an original descriptor, stack-linkage word, and so 

forth. Software requires that references generally not be stored in segments or 

activation records with longer lifetime than the referent. 

All IndexedDDs are treated as SingleDDs (char_index is ignored for an IndexedCharDD). 

Overwrite operators store single words; OVRD and OVRN are oblivious to double 

precision. If the store object is double precision, only the first word is stored, with its tag 

of two. If the reference addresses a tag-2 word, only that word is overwritten; its 

successor word is unchanged. Note that each case can produce an unpaired double 

precision word in memory. 

OVRD 

An overwrite operation is performed. Both the Initial Reference and the store object are 

deleted from the stack. 

 

 

ref: SIRW, IDD, ASRW 

Top-of-stack 

 


object: any Null 

 

 

OVRN 

An overwrite operation is performed. The store object is left unchanged on top of the 

stack and the Initial Reference is deleted. 

 

 


Top-of-stack 

 


object: any object 

 

 

RDLK 

RDLK is identical to OVRD, except that the word previously occupying the target location 

is left as the stack result. A tag of 2 in the result is set to 0. Only the single target word 

will be fetched. 

5–62 6878 7530–007

Operator Set 

 

 


Top-of-stack 

 


object: any target: word 

 

 

RDLK is a synchronization primitive. The following requirements must be met by all 

operating systems and by any other processing elements (such as I/O or 

communications processors) that share the system memory and use the RDLK 

convention for synchronization: 

1. RDLK reads the former contents and writes the new contents of the referenced 

word as an indivisible operation; no other processor can access the referenced word 

between the read and write steps of a RDLK operator. 

2. Store operations for each processor effectively occur in order. That is, if a code 

stream on one processor initiates stores into location A and then into location B, any 

processor that finds the new value at B (with RDLK) and subsequently examines A 

must find the new value at A. 

3. No data-fetch memory operation that follows the RDLK in the dynamic code stream 

of a processor may take place until after the RDLK operation. 

Statements 2 and 3 restrict the ability of a system to reorder the manipulation of 

independent pieces of the system, such as the contents of different memory locations. 

Character Reference Evaluation Operators 

The character reference evaluation operators evaluate descriptor references to a single 

character target. They differ from “word” reference evaluation operators both in 

addressing only a single character, and in accepting only IndexedDDs, not IRWs, as final 

references. They differ from data array operators because they process only a single 

character, and (unlike single character edit inserts) because their argument order and 

operator context have none of the unique features of pointer or edit operators. 

All of these operators accept an IndexedDD reference. The character size is determined 

by the element_size of the reference, with a WordDD (SingleDD or DoubleDD) being 

treated as 8-bit with a char_index equal to zero. The target character must be contained 

in a word with operand tag. The object input to the store operators, and the result of the 

load operators, is a character of appropriate size right justified in a single precision 

operand. 

LODC 

LODC extracts the character referenced by an IndexedDD argument, leaving the 

character right-justified with zero fill in a single precision operand on top of the stack. 

 

Top-of-stack 

ref: IDD sp(char) 


 

6878 7530–007 5–63

Operator Set 

STCD 

STCN 

For STCD and STCN, the reference and the operand are required on top of the stack, in 

either order. STCD deletes both the reference and the operand from the stack: 

 

 

object: sp(char) 

Top-of-stack 

 


ref: IDD Null 

 

 

 

 

ref: IDD 

or 

 

 

object: sp(char) Null 

 

 

STCN deletes the reference but leaves the operand unchanged on top of the stack: 

 

 

object: sp(char) 

Top-of-stack 

 


ref: IDD object 

 

 

 

 

ref: IDD 

or 

 

 

object: sp(char) object 

 

 

STCx stores into the character location referenced by the IndexedDD argument, 

selecting the corresponding character in the right-justified position of the single precision 

operand argument. The tag of the destination word will be persevered. STCD will delete 

both arguments from the stack, while STCN will delete the IndexedDD but will leave the 

operand unchanged in TOS. 

5–64 6878 7530–007

Processor State Operators 

Operator Set 

This section describes operators that interact with processor state, primarily the state of 

the currently executing code stream and the state of the stack in which the processor is 

running. 

Code Stream Pointer Distribution 

The processor code stream pointer is initialized by the distribution of PCW or RCW code 

stream pointer components. 

1. The PSN (Program Segment Number) is set from the ASD_number field in the PCW 

or RCW. 

2. The PWI and PSI are set from the corresponding fields in the PCW or RCW. PWI 

must be in the range {0 to L-1}, where L is the length of the code segment; PSI must 

be in the range {0 to 5}. 

Branching Operators 

Branching operators provide for altering the processor's code stream pointer component. 

They may change the point of execution in the current code segment or establish a new 

code segment with an initial point of execution. 

Branches may be conditional or unconditional. Conditional branches alter the code 

stream pointer or continue sequential execution depending upon the Boolean 

interpretation of a stack argument. 

Branching operators are classified as static or dynamic branches and are discussed in the 

following paragraphs. 

Static Branches 

Static branches always point within the current code segment. That point is indicated by 

a two-syllable parameter: 

 

Operator op_ : 

BRxx : op_pwi 

format: psi : 

 

: 

3 : 13 

The high-order three bits of the parameter are interpreted as the new PSI value and the 

low-order 13 bits as the new PWI value. The maximum valid op_pwi is one less than the 

length of the current code segment; the maximum valid op_psi is five. 

6878 7530–007 5–65

Operator Set 

BRUN 

Processor registers PSI and PWI are set from the parameter and the processor is 

conditioned to execute next the operator at that point in the current code segment. 

BRTR 

BRFL 

The top-of-stack argument must be an operand; it is interpreted as a Boolean value. If 

BRTR finds it to be True or BRFL finds it to be False, processor registers PSI and PWI 

are set from the parameter and the processor is conditioned to execute next the 

operator at that point in the current code segment. Otherwise, sequential execution 

continues. 

Top-of-stack 

 

transformation opnd(Boolean) Null 

 

 

Dynamic Branches 

Dynamic branches take their code stream pointer values from a branch destination item 

on top of the stack. They may branch to a computed point within the current code 

segment or to a point in an arbitrary code segment. 

::= {operand, PCW, initial reference} 

::= {SIRW} 

::= PCW 

SIRW 

Branching within the current code segment is indicated if the branch destination item is 

an operand. It is integerized with rounding (RAI function), if required, to produce a 14-bit 

integer, which is interpreted as the code segment index in units of half-words (three 

syllables): 

dyn_pwi [13:13] New PWI value 

dyn_half_word [ 0: 1] The new PSI value is dyn_half_word * 3 

The largest valid dyn_pwi is one less than the length if the current code segment. 

Branching to a point in an arbitrary code segment is indicated if the branch destination 

item is a PCW or an SIRW to a PCW. PCW.lex_level must match the current value of LL. 

The PCW code stream pointer is distributed as specified under "Code Stream Pointer 

Distribution" in this section. 

5–66 6878 7530–007

DBUN 

A branch destination argument is required on top of the stack. 

Top-of-stack 

 

transformation: dest: opnd(integer), PCW, SIRW Null 

 

 

DBTR 

DBFL 

Operator Set 

The branch destination argument is required on top of the stack. The argument second 

from top-of-stack must be an operand; it is interpreted as a Boolean value. If DBTR finds 

it to be True or DBFL finds it to be False, a branch is executed using the top of the stack 

branch destination item exactly as in DBUN. Otherwise, sequential execution continues. 

 

Top-of-stack 

dest: opnd(integer), PCW, SIRW 


 

 

opnd(Boolean) Null 

 

 

Stack Frame Operators 

Operators in this group provide for procedure entry and exit and the creation and 

destruction of stack frames. 

Procedure Entry Operators 

The sequence of operations in normal procedure invocation has already been outlined: 

1. Perform a Mark Stack operation. 

2. Place a reference to the code onto the stack. 

3. Place any parameters onto the stack. 

4. Perform an Enter operation. 

5. Place objects onto the stack to extend the new AR. 

MKST 

Mark Stack operators mark the stack for the beginning of a new stack frame by creating 

at the top of the expression stack an incipient activation record linked into the historical 

chain. 

MKST builds a HISW, ENVW pair on top of the stack. The HISW is linked at the head of 

the historical chain and records the values of the Boolean accumulators; the ENVW is 

inactive and is a copy of the HISW. 

6878 7530–007 5–67

Operator Set 

 

 

inactive ENVW 

Top-of-stack 

Null 


HISW F 

 

 

The displacement between the new ENVW location and the base of the current stack 

must be in the range {1 to 2**16-1}. 

F is set to point at the new HISW on the stack. 

MKSN 

This operator is functionally equivalent to the MKST operator and is subject to the 

following rules: 

1. The immediate next operator in the code stream must be one of the name call 

operators: NAMC, LNMC, NMC0, NMC1, NMC2, or NMC3. 

2. The address couple in the name call operator must be the initial reference for the 

corresponding ENTR. 

3. With two exceptions, the addressing environment, reference chain, and code 

segment addressing must remain the same when the corresponding ENTR is 

executed as when the MKSN was executed. Code Segment Addressing refers to 

the components of the PCW and ASD that are used to address the code segment; 

the term also includes the status (untouched, absent, present) of the segment. The 

exceptions are: 

• The reference chain does not yield a PCW. As a result of the ensuing interrupt, 

the reference chain, PCW, and code-segment addressing are subject to 

modification. 

• Another mark-stack operation occurs, either explicitly or via an interrupt. In this 

case, code segment status (untouched, absent, or present at a specific address) 

is subject to change, but the addressing environment, reference chain, and PCW 

must not change. 

4. Between the execution of the MKSN and the subsequent execution of the 

corresponding ENTR, the stack linkage remains valid and inactive, however, the 

contents of the ENVW and the entire SIRW/PCW location are undefined. 

MKSN is obsolete, superceded by MKST. 

IMKS 

IMKS creates an incipient activation record exactly as does MKST (mark stack), except 

that the new HISW, ENVW pair is inserted beneath the two top of stack items. There 

must be at least two items in the expression stack at the start of an IMKS operation. 

5–68 6878 7530–007

Operator Set 

 

 

TOS 

 

 

 

TOS: any TOS2 

Top-of-stack 

 


TOS2: any Inactive ENVW 

 

 

 

HISW F 

 

 

ENTR 

The initial stack state for ENTR assumes prior execution of a Mark Stack operator and 

placement of a procedure reference onto the stack. S–1 > F > D[LL]+1 must be true, an 

HISW and an inactive ENVW are required at the F and F+1 stack locations, and an Initial 

Reference is required at the F+2 stack location. 

 

: : : : 

Stack-state : optional : : optional : 

: : : : 

transformation: : parameters : : parameters : 

: : : : 

 

 

SIRW, PCW RCW 

 

 

 

inactive ENVW entered ENVW D[LL] 

 

 

 

F HISW HISW F 

 

 

::= {SIRW, 

} 

::= {PCW} 

SIRW SIRW 

 

ENTR consists of the following functional tasks: 

1. Activate the ENVW, inserting it at the head of the appropriate environmental chain: 

a. ENTR forms an Environmental Link to address the base of the global AR; this 

Environmental Link is inserted into the ENVW to complete the environmental 

chain that defines the addressing environment of the new procedure. 

6878 7530–007 5–69

Operator Set 

b. The global AR is identified by the form of the procedure reference. If the PCW is 

the initial reference or if the PCW is directly referenced by the address couple in 

a name call operator immediately following the most recent MKST or MKSN, the 

global AR is the one at lex level L = PCW.lex_level-1 in the initial addressing 

environment. In these cases, an Environment Link to the global AR is 

constructed by implicit invocation of the name call operator with the address 

couple (L,0). Otherwise, the final reference to the PCW is an SIRW, whose 

Environment Link points directly to the global AR. 

c. The word at the base of the global AR must be an entered ENVW. If the PCW is 

the initial reference, the PCW.lex_level must be in the range {1 to LL+1}. 

2. Preserve the code stream pointer and related state in an RCW: 

a. When entry occurs from a code segment, whether by explicit invocation of 

ENTR or by accidental entry or interrupt, the operation builds an RCW containing 

the processor code stream pointer and the values of LL and the CS (control 

state) Boolean. For explicit ENTR, the RCW code stream pointer designates the 

syllable following ENTR. For accidental entry (ENTR invoked by aACCE), the 

code stream pointer designates the operator invoking aACCE. For interrupt 

entry, the code stream pointer is determined by the specific interrupt situation. 

b. The RCW is stored in place of the Initial Reference. 

3. Initialize processor state for the new procedure: 

LL is set from PCW.lex_level and D[LL] is set from F+1 to address the base of the 

activation record. The processor CS Boolean is set from PCW.control_state. 

Display registers are updated to reflect the new addressing environment. If the new 

PCW reference was the address couple in a name call operator immediately 

following the most recent MKST or MKSN, or the Initial Reference was a PCW, no 

update is necessary, since the global AR of the new activation record is already in 

the addressing environment. Otherwise, display update begins at D[LL–1], the new 

global AR. 

The expression stack is appended to the new activation record, making any 

procedure parameters accessible. 

The processor code stream pointer state is initialized from the PCW. 

aACCE 

The common action aACCE is invoked by some reference-chain evaluation operators to 

evaluate a PCW. The action is automatic invocation of the parameterless procedure 

(function) defined by the PCW; it is defined as three steps: 

1. Invoke MKST. 

2. Place the reference to the PCW onto the stack. 

3. Invoke ENTR. 

The accidental entry and subsequent return leave the processor executing the operator 

that initiated the accidental entry. (Unlike explicit ENTR, which builds an RCW 

referencing the successor operator, aACCE points the RCW at the invoking operator.) 

The invoking operator provides the value for rs. In particular, value-call operators set rs to 

1 to cause reentry in restart state. 

5–70 6878 7530–007

Procedure Exit Operators 

Operator Set 

There are three operators for deleting a stack frame and reinstating the prior topmost 

stack frame and its code stream. 

EXIT terminates a subroutine and leaves no result 

RETN terminates a function and leaves the top of stack item as 

a result 

RTN2 terminates a procedure that leaves two top-of-stack 

results 

These operators perform the Exit operation, which deletes the topmost stack frame from 

the stack and restores processor state for the prior topmost stack frame. The base 

location of the topmost activation record is addressed by D[LL] and the prior topmost AR 

is located as the first entered AR below D[LL]. 

F must be equal to D[LL]-1 at the beginning of an Exit operation; the topmost activation 

record must be entered, not incipient. The HISW addressed by F is also deleted. 

If the stack linkage of the topmost activation record has the block_exit bit set, the Exit 

operation is not performed; a Block Exit service interrupt is generated instead. 

The topmost stack frame is deleted from the stack by setting the top of stack pointer at 

the first word below the stack linkage. At the start of the operation, S > D[LL] must be 

true (not counting any return arguments). The F register is set to point at the first HISW 

on the historical chain headed by the activation record being exited. LL is set from the 

value saved in the RCW. D[LL] is reset to address the base of the prior topmost 

activation record. If the new F designates an incipient AR, the historical chain is 

traversed until an entered AR is found. The CS (control state) Boolean and the Boolean 

accumulators are restored by distributing values saved in the stack linkage of the original 

stack frame. Display registers are updated to reflect the new addressing environment; 

the environmental chain is traversed beginning at D[LL]. 

The processor code stream pointer is initialized from the RCW. If rs is set, the processor 

is conditioned to execute in restart mode the operator addressed by the new codes 

stream pointer. 

EXIT 

The EXIT operator performs an Exit operation for a procedure that returns no value on 

the stack. 

 

Stack-state : : 

: topmost : 

transformation: : : 

: stack frame : 

 

D[LL] linkage Null 

F 

 

6878 7530–007 5–71

Operator Set 

RETN 

RETN performs an Exit operation for a procedure that returns a result on the stack. It 

retains the initial top-of-stack item and pushes it back onto the expression stack after the 

topmost stack frame is deleted. 

 

 

TOS: any 

 

 

Stack-state : : 

: topmost : 

transformation: : : 

: stack frame : 

 

D[LL] linkage TOS 

F 

 

RETN requires an item from the expression stack. In user programs, the item should be 

an operand or a reference to some object that is global to the procedure being exited. 

Trusted software must prevent the return of a copy DD referencing a segment being 

deallocated by the exiting of this block. 

RTN2 

RTN2 performs an Exit operation for a procedure that returns two results on the stack. 

The topmost two items in the topmost stack frame are placed in the same order at the 

top of the resumed stack frame. RTN2 requires two items from the expression stack. 

 

 

TOS: any 

 

 

 

TOS2: any 

 

 

Stack-state : : 

: topmost : TOS 

transformation: : : 

: stack frame : 

 

D[LL] linkage TOS2 

F 

 

5–72 6878 7530–007

Assertion Operators 

Operator Set 

The assertion operators, ASRT and AVER, require and consume one operand on the 

stack. The argument is interpreted as a Boolean value. If it is False, a False Assertion 

interrupt is generated; the argument value is available to software for analysis. If the 

code stream is resumed by exiting from the interrupt procedure, the argument is gone 

from the stack and the subsequent operator is invoked. 

Top-of-stack 

 

transformation: opnd(Boolean) Null 

 

 

ASRT 

The ASRT operator performs an assertion operation. It has a one-syllable code 

parameter, which is available to software if a False Assertion interrupt is generated. 

 

Operator 

ASRT code 

format: 

 

AVER 

The AVER operator performs an assertion operation; it has no code stream parameter. 

(The verb aver is defined in Webster's New Collegiate Dictionary as "to verify or prove to 

be true..., to declare positively"; it is not an acronym or abbreviation.) 

Top-Of-Stack Operators 

These operators delete, duplicate, or reorder top-of-stack items. There is no restriction 

on the type of stack item that will be acted upon, however, as operator arguments, the 

items must be in the expression stack to avoid Stack Underflow interrupts. Note that an 

item may comprise either one or two words. 

DLET 

DLET requires one item on top of the stack and deletes it from the stack. 

Top-of-stack 

 

transformation: any Null 

 

 

6878 7530–007 5–73

Operator Set 

EXCH 

EXCH requires two items on top of the stack and interchanges their order in the stack. 

 

 

item1: any item2 

Top-of-stack 

 



 

 

DUPL 

DUPL requires one item on top of the stack, creates an exact duplicate of it, and leaves 

both items on top of the stack. 

 

 

item1 

 

 

Top-of-stack 



 

RSUP 

RSUP requires three top of stack items. The third from top item is rotated up to become 

the top of stack item. 

 

 


 

 

Top-of-stack 



 

 


 

 

5–74 6878 7530–007

RSDN 

Operator Set 

RSDN requires three top of stack items. The top item is rotated down to become the 

third from top of stack item. 

 

 


 

 

Top-of-stack 



 

 


 

 

Processor-State Manipulation Operators 

Operators in this group directly affect various elements of processor state, often reading 

state to the top of stack or setting state from the top of stack. 

DEXI 

DEXI conditions the processor to ignore all external interrupts and sets the processor CS 

Boolean to one (control state). The stack is unaffected. 

DEXI is partially restricted; DEXI and EEXI may be safely used only around short 

segments of code that must be executed atomically and are of short duration. 

EEXI 

EEXI conditions the processor to respond to external interrupts and resets the processor 

CS Boolean to 0 (normal state). If any external interrupt is pending when EEXI is 

executed (in control state), the interrupt occurs immediately following the EEXI operator, 

even if the immediate successor operator is DEXI. 

EEXI is partially restricted; it is used only as a companion to DEXI. 

ROFF 

ROFF leaves on top of the stack the Boolean value of OFFF (overflow flip-flop) and then 

unconditionally resets OFFF to false. 

 

Top-of-stack 

Null sp(Boolean) 


 

RTFF 

RTFF leaves on top of the stack the value of TFFF as a Boolean operand, True or False. 

The top of stack transformation is the same as for ROFF. 

6878 7530–007 5–75

Operator Set 

SXSN 

SXSN requires an operand on top of the stack. SXSN sets EXTF (EXTernal sign flip-flop) 

to the value of bit 46 of the top of stack item. The operand is left unchanged on the 

stack. 

 

Top-of-stack 

TOS: operand TOS 


 

RTOD 

RTOD leaves on top of the stack a 36-bit integer containing the value of the real time of 

day clock. The range of values is {0 to 2**36-1} in units of 2.4 microseconds, but is 

subject to change in later ClearPath MCP systems. 

 

Top-of-stack 

Null sp(integer) 


 

RSNR 

RSNR leaves on top of the stack a single_integer containing the SNR value. 

 

Top-of-stack 



 

5–76 6878 7530–007

Data Array Operators 

Operator Set 

Operators in this group perform functions on arrays specified by data descriptor stack 

arguments. The functions applied generally consist of sequential processing of one or 

more arrays of word or character elements. Termination occurs when an element length 

has been exhausted or when some condition is satisfied. 

Data in one of the argument arrays may be modified, the arrays may be processed in 

order to produce a result, or both actions may occur. Results are indicated by items left 

on top of the stack or by the setting of one or more processor Boolean accumulators. 

Array operators typically accept IndexedDDs as arguments. For an operator to access the 

data, the actual segment must be present. 

Paged Array Operations 

In general, arrays may be paged segments. The exception is that edit tables must be 

unpaged. (I/O subsystems, which are not specified here, typically require unpaged 

buffers.) 

A service interrupt (Touch Reference or Absent Data) occurs when an attempted page 

switch encounters an untouched or absent page. (Error interrupts can also occur at a 

page boundary if the ASD or page table structure is incorrect.) A characteristic of the 

Data Array operators is that a service interrupt can occur in mid-operation; such an 

occurrence is generically called a page boundary interrupt, a term that also includes 

Source and Destination Boundary interrupts. After the service has been performed 

(necessary segments are present), the operation is resumed. In general, the processor 

takes up where it stopped, although some operators can be simply repeated from the 

beginning. 

Except for the cases previously noted, Data Array operators automatically attempt to 

switch to the next page when an actual segment is exhausted. 

It is convenient to formalize all adjustment of descriptor index values as using aAPIX to 

apply a suitable increment; the common action switches pages as needed. 

6878 7530–007 5–77

Operator Set 

Searching Operators 

There are two searching operators: SRCH (masked search for equal) and BMS (bounded 

masked search for equal). Each search an array backwards for the first word that is 

bitwise equal to a target value after both the word and target value have been masked. 

SRCH 

SRCH scans an array called the domain, which is a virtual segment. The array is searched 

from an indexed starting point back towards the base for a word that matches a target 

value in selected bits. Any or all of the 56 bits (word, extension, and tag) may be 

matched. The result is a single_integer that is the virtual index of the matching word or - 

1 if the search fails. 

SRCH requires three arguments on top of the stack: the search domain, the mask, and 

the target value. 

 

 

domain: IndexedSingleDD 

 

 

Top-of-stack 

mask: any(bit-vector) 


 

 

targ: any(bit-vector) sp(integer) 

 

 

The domain argument must be an IndexedSingleDD; reindex must be enabled. 

Both the mask and target value are bit vectors of length 56. The target value is logically 

ANDed with the mask before it is used for comparison. The second word of any double 

precision target value or mask is ignored. 

The word referenced by the IndexedSingleDD is logically ANDed with the mask and 

compared to the (masked) target value. If a matching word is found, its index (relative to 

the virtual segment) is left on the stack as the SRCH result. If there is no match and the 

index is nonzero, the index is decremented by one and the search continues. If there is 

no match and the index is zero, the segment is exhausted and the failure result is 

returned. 

5–78 6878 7530–007

BMS 

Operator Set 

BMS is a variation of SRCH, with an additional argument that provides an upper bound 

on the length (number of words) of the search. The length argument appears topmost on 

the stack: 

 

 

length: opnd(integer) 

 

 

Top-of-stack 

domain: IndexedSingleDD 


 

 

mask: any(bit-vector) 

 

 

 

targ: any(bit-vector) sp(integer) 

 

 

The length must be an operand. It is integerized with the RaI function, if necessary; its 

integer magnitude must not exceed MaxLen. 

The domain, mask, and target arguments; the failure value; and the search algorithm are 

as defined for SRCH with the exception of the following: 

• The operator terminates and returns the failure result if the length is zero or negative 

at the beginning of any iteration (including the first) 

• The length is decremented after each word is examined 

• It is an error if the virtual segment is exhausted before the length is decremented to 

zero 

6878 7530–007 5–79

Operator Set 

Pointer Operators 

Pointer operators handle sequences of word or character elements in data arrays. There 

are pointer operators for scanning, transferring, comparing, and editing the element 

sequences in various methods. Some pointer operators handle only a source or a 

destination sequence, both a source and a destination sequence, or two source 

sequences. Sequential processing terminates when a length (element count) is 

exhausted. Other pointer operators, called enter-edit operators, serve to invoke one or 

more instances of another class of pointer operators, called edit-mode operators. 

Typical pointer operators require initial stack arguments that specify the length, the 

source element sequence, and the destination element sequence. A source or 

destination descriptor defines the first element of the target sequence; such a descriptor 

is generally called a pointer. More formally, pointer (in the context of data descriptors) is 

defined as the type union IndexedCharDD or IndexedWordDD. A source element 

sequence can be contained in an operand or designated pointer; a destination sequence 

is always designated by a pointer. 

Some operators (pack, input convert, string isolate) read a source and generate a result 

operand on the stack. These stack results are not defined to be destinations. 

The char_index of an IndexedCharDD must not exceed five or eleven for EBCDIC or hex, 

respectively. 

Element_size Conventions 

The element size for the source and/or destination sequence can be specified by the 

element_size in the IndexedCharDDs, inferred by default, or fixed by the operator. Only 

the translate operator can manipulate source and destination sequences of different 

element sizes. The word-transfer operators always operate on single words, however, 

they can accept indexed descriptors of any valid element_size. The unpack operators 

require a source operand and handle it as hex. 

All pointer operators, except for word-transfer, deal with either 4 or 8-bit characters. The 

following element_size adjustments are made (but the operand source of an unpack 

operator is always 4-bit): 

• If there are both source and destination arguments (or two source arguments), and 

only one is an IndexedCharDD, the element_size of the IndexedCharDD is applied to 

the other argument. 

• If there is no IndexedCharDD argument, then any source or destination is assumed 

to be EBCDIC. 

• When a character element_size is applied to a source or destination word descriptor, 

that argument effectively becomes an IndexedCharDD; the index must not exceed 

2**16-1. 

5–80 6878 7530–007

Operator Set 

For word-transfer operators, the element_size specified in the source and destination 

descriptors is unaltered and the operation handles single words. If an IndexedCharDD is 

used as source or destination and the char_index is nonzero, the descriptor is adjusted 

by setting char_index to zero and incrementing word_index; the resulting word index 

must not exceed 2**16-1. 

For all pointer operators except word-transfer and translate, if the source and destination 

arguments are both IndexedCharDDs, the element_size values must be equal. 

Segment Boundary 

The term segment boundary refers to the edges of a virtual segment. A segment 

boundary is detected when a pointer operator attempts to access an array element 

outside the source or destination virtual segment. This detection causes the processor to 

generate an error or service interrupt. 

Segment boundaries are determined from information in the ASDs (and in the page table 

for paged segments). A non-Data Word within the segment is reported separately via an 

error interrupt. 

A segment boundary is not detected after the length has been exhausted, by comparedelete 

operators after a mismatch has been detected, or by scan or conditional transfer 

operators after a source character has failed to satisfy the condition. 

Length Argument 

When a pointer operator is invoked in initial mode, the comments in the subsequent 

paragraph apply. If a pointer operator is resumed in restart mode, the length argument 

must be updated by the interrupted operator. (In some restart situations, a length of zero 

is significant.) 

The length argument must be an operand. It is integerized with rounding (RaI function) if 

required; the integer magnitude must not exceed MaxInx. 

A negative length value is equivalent to zero. If length is less than or equal to zero, all 

pointer operators terminate without accessing any source element or transferring any 

destination element, no segment boundary is detected, and no service interrupts are 

generated. (The enter-single-edit operators do not terminate for zero-length input; rather, 

any edit operators that require a length do so.) 

Source Argument 

The source argument must be an operand or a DD (indexed or unindexed) of any valid 

element_size. 

A source IndexedDD must have reindex enabled in all cases. All the elements accessed 

in the source sequence must be in operands. 

All pointer operators reject an attempt to access a source element outside the source 

segment. For certain of these operators that unconditionally transfer data to a 

destination, the interrupt is a Source Boundary service request when the attempted 

access is to fetch the first element beyond the source virtual segment. 

6878 7530–007 5–81

Operator Set 

A source operand sequence begins with the high order character of the operand; it is 

interpreted according to element_size conventions defined above as EBCDIC sequence 

of 6 (or 12) characters or a hex sequence of 12 (or 24) characters, for a single (or double) 

precision operand, respectively. The operand is concatenated with itself as required to 

form a sequence of indefinite length. 

Short Source Operators 

The string-isolate, pack, and input-convert operators are special in that the source 

sequence is short (never more than 25 characters) and the result is left on the stack as 

an operand rather than be moved to a destination sequence. Some of these operators 

interpret one character or one zone field as a sign. 

If a short-source operator is interrupted and the code sequence is subsequently 

resumed, the operator is repeated from the beginning. 

Destination Argument 

The destination argument must be a DD (indexed or unindexed) of any valid 

element_size; a destination IndexedDD must have reindexed enabled. 

Any word modified in the destination sequence of a character transfer operator must 

contain an operand; any destination word written by a word transfer operator must 

contain a Data Word. Character transfer operators preserve the tag and extension of the 

destination word; word transfer operators copy the tag and extension of the source word 

into the destination word. 

An operator is said to require a destination if a destination stack argument is specified, 

except for the Enter Single Edit operators. These operators require a destination if the 

subsequent edit operator conditionally or unconditionally transfers data. All operators that 

require a destination require a write enabled destination pointer. 

All pointer operators reject an attempt to access a destination element outside the 

destination sequence. If the attempt is to store into the first element beyond the 

destination segment, the interrupt is a Destination Boundary service request. 

Source1 and Source2 Arguments 

The compare operators process two sources, rather than a source and a destination. 

Source2 is a source defined previously. Source1 takes the place of a destination; it must 

be a DD (not an operand). Both source IndexedDD cases require that reindex be enabled. 

Overlapping Source and Destination 

A source and destination are said to overlap if both arguments are DDs into the same 

segment and the displacement (index difference) between them is less than the 

effective length (number of elements transferred). 

The effect of an overlapped unconditional word or character transfer depends upon the 

direction and magnitude of the displacement. In the following, D represents the 

displacement expressed as destination element index minus the corresponding source 

element index. L represents the transfer length. 

5–82 6878 7530–007

Operator Set 

D

Operator Set 

A source or destination descriptor is updated as an indexed descriptor that references 

the next source or destination element that would have been processed. The updated 

descriptor reflects any adjustments made according to the element_size conventions 

previously defined. Word-transfer operators may adjust the char_index and word_index 

values; all other operators change any IndexedWordDD into an IndexedCharDD. These 

adjustments occur even when length less than or equal zero, but they are undefined for 

the special case of RSTF introduced by EXPU or EXSU. 

An updated descriptor from a forward-acting operator can designate the first element 

beyond the segment. 

The field-width limits in a descriptor are 2**16-1 for the word_index field in an 

IndexCharDD and 2**20-1 for the index field in an IndexedWordDD. If the word index 

value to be updated into a descriptor exceeds the limit, an error interrupt is generated. 

The interrupt is reported at any point in the processing sequence where the word index 

exceeds the limit. 

Most pointer operators can be interrupted (for example, at a page boundary) in such a 

way that the operation can be resumed where it stopped. Both update and delete 

operators are subject to such interruption; the stack arguments are configured for 

resuming the operator in initial (for short-source operators) or restart (for all other pointer 

operators) mode. In restart mode, the original arguments are left on the stack with a 

progress count included in the restart information. 

Unconditional Character-Transfer Operators 

Unconditional character transfer operators transfer hex or EBCDIC characters from the 

source to the destination. The number of characters transferred is specified by the 

length. TFFF is left in an undefined state. 

TUND 

 

 

len: opnd(integer) 

 

Top-of-stack 

 

transformation source: pntr, opnd 

 

for TUND: 

 

dest: pntr Null 

 

 

5–84 6878 7530–007

TUNU 

 

 


 

Top-of-stack 

 

transformation source: pntr, opnd source’ 

 

for TUNU: 

 

dest: pntr dest’ 

 

 

Character Relational Operators 

Operator Set 

Character relational operators sequentially apply a relational comparison of each source 

character to a delimiter character supplied by a stack argument until the length is 

exhausted or a relation fails. For the scan and transfer operators, TFFF indicates the 

cause of termination: it is reset to 0 if a relation fails and set to 1 if the length is 

exhausted (all source characters satisfy the relation or the initial length is less than or 

equal to zero). For the string copy operator, TFFF is left undefined. 

The delimiter argument must be a single precision operand; it is interpreted as a single 

right-justified character (EBCDIC or hex according to the effective element size of the 

source); all bits in the delimiter word except those in the delimiter character are ignored. 

The binary value of each source character is compared to the binary value of the 

delimiter character. The operator names specify the relation of the source character to 

delimiter that must hold for the operation to continue. For example, the SLSU operator 

scans across source characters less than the delimiter. 

6878 7530–007 5–85

Operator Set 

Scan Operators 

Character relational scan operators sequentially compare each source character to the 

delimiter character as defined previously. In Level Delta and Epsilon, SxxD is required to 

be immediately followed by RTFF, and TFFF is left in an undefined state. 

SEQD (scan while equal delete) 

SNED (scan while not equal delete) 

SGTD (scan while greater delete) 

SGED (scan while greater or equal delete) 

SLED (scan while less or equal delete) 

SLSD (scan while less delete) 

 

 

delim: sp(char) 

 

Top-of-stack 

 

transformation len: opnd(integer) 

 

for SEQD, etc.: 

 

source: pntr, opnd Null 

 

 

SEQU (scan while equal update) 

SNEU (scan while not equal update) 

SGTU (scan while greater update) 

SGEU (scan while greater or equal update) 

SLEU (scan while less or equal update) 

SLSU (scan while less update) 

 

 


 

Top-of-stack 

 

transformation len: opnd(integer) len’ 

 

for SEQU, etc.: 

 

source: pntr, opnd source’ 

 

 

5–86 6878 7530–007

Transfer Operators 

Operator Set 

Character relational transfer operators sequentially compare each source character to the 

delimiter character as defined previously. Each source character that satisfies the relation 

is transferred to the destination sequence. 

TEQD (transfer while equal delete) 

TNED (transfer while not equal delete) 

TLED (transfer while less or equal delete) 

TLSD (transfer while less delete) 

TGTD (transfer while greater delete) 

TGED (transfer while greater or equal delete) 

 

 


 

Top-of-stack 

 


 

for TEQD, etc.: 

 

source: pntr, opnd 

 

 

 


 

 

TEQU (transfer while equal update) 

TNEU (transfer while not equal update) 

TGTU (transfer while greater update) 

TGEU (transfer while greater or equal update) 

TLEU (transfer while less or equal update) 

TLSU (transfer while less update) 

 

 


 

Top-of-stack 

 


 

for TEQU, etc.: 

 


 

 

 


 

 

6878 7530–007 5–87

Operator Set 

SCPY 

The string copy operator is identical to TNED, with three exceptions: 

• A source character which is equal to the delimiter will be transferred, even though it 

terminates the operator. 

• The number of characters transferred which are unequal to the delimiter will be left 

as a result in TOS. 

• TFFF will be left undefined. 

 

 


 

 

 


Top-of-stack 

 



 

 

 

dest: pntr xfer count 

 

 

Character-Sequence Compare Operators 

Character sequence compare operators apply a relational comparison of the source1 

sequence to the source2 sequence. The operator name specifies the relation being 

tested. These operators are required to be followed by RTFF, and TFFF is left in an 

undefined store. 

The binary values of each corresponding source1 and source2 character are compared. 

The two sequences are equal if, and only if, each source1 character is equal to the 

corresponding source2 character for the specified length or the initial length is zero. 

Source1 is strictly less (greater) than source2 if, and only if, for the first (left-most) pair of 

unequal characters, the source1 character is strictly less (greater) than the source2 

character. 

5–88 6878 7530–007

The following operators terminate when the actual relation is determined. 

CEQD (compare characters equal delete) 

CNED (compare characters not equal delete) 

CGTD (compare characters greater delete) 

CGED (compare characters greater or equal delete) 

CLED (compare characters less or equal delete) 

CLSD (compare characters less delete) 

 

 


 

Top-of-stack 

 

transformation source2: pntr, opnd 

 

for CEQD, etc.: 

Null 

source1: pntr 

 

 

Operator Set 

The character sequence compare operators are obsolete, superceded by CREL ZERO 

Numeric Relational sequence.. 

Character Sequence Relation Operators 

These operators are similar to the character sequence compare operators, except that 

they determine the exact relation between the two character sequences and report the 

result on the top of stack, rather than in TFFF, which is left undefined. 

 

 


 

 

Top-of-stack 

source2: pntr, opnd 


 

 

source1: pntr result 

 

 

The result defines the relation between the two sequences as follows: 

source1 < source2: –1 

source1 = source2: +0 

source1 > source2: +1 

CREL 

CREL determines the relation between two character sequences, for the entire length 

indicated by the length argument. It terminates as soon as the relation is determined by 

unequal characters. 

6878 7530–007 5–89

Operator Set 

SCMP 

SCMP performs the same comparison as CREL, but terminates early if a null (zero) 

character is encountered in either sequence, reporting the relation determined up to that 

point. If a null character is encountered simultaneously in both strings, the result of equal 

is returned; otherwise, the string containing the first null character is reported as less. 

Character sequence relationals supplant old comparisons 

The character sequence relation operators avoid the need to issue two character 

sequence compare operators to determine the precise relation between two sequences, 

as the result can be duplicated on the stack and various relations tested: 

source1 = source2: not BOOLEAN(result) 

source1 source2: BOOLEAN(result) 

source1 < source2: result < 0, or BOOLEAN( result . [46:1] ) 

source1 source2: result > 0 

source >= source2: result geq 0, or not BOOLEAN (result . [46:1]) 

SCMP may take the place of at least two pointer operators (a scan update followed by at 

least one compare) when the length of one or both sequences is unknown (is delimited 

by a null character). Note, however, that CREL will typically perform better than SCMP 

where applicable; including the case where only one length is known, but that string is 

also known not to contain a null character. 

Character Set Membership Operators 

Character set membership operators test source characters for membership in a 

character set supplied by a stack argument. The relations applied are inclusion and 

exclusion. Source characters are sequentially tested until the relation fails or the length is 

exhausted. TFFF indicates the cause of termination: It is reset to 0 if a relation fails and 

set to 1 if the length is exhausted (all source characters satisfy the membership criterion 

or the initial length is less than or equal to zero). 

The character set argument must be an IndexedSingleDD, which designates the first 

word of the character set. Reindex must be enabled in this descriptor. Every word 

accessed in the set must be an operand. Every word accessed in the set must lie within 

the designated virtual segment. 

The character set is interpreted as a bit vector indexed by the source character. If the 

selected bit is 1, the character is included in the set; otherwise, it is excluded from the 

set. The bit is located by the following expression, where Set represents the character 

set argument and SetSeg the segment designated by that argument: 

SetSeg[Set.index+WordIndex(c)].[BitIndex(c):1] 

5–90 6878 7530–007

Operator Set 

WordIndex and BitIndex are computed from the binary representation of the source 

character (c) as follows: 

EBCDIC WordIndex = value of three high-order bits 

BitIndex = 31 - (value of five low-order bits) 

hex WordIndex = 0 

BitIndex = 31 - (4-bit value) 

In the following operator names, the relation "while source included in set" is called while 

true and "while excluded from set" is called while false. 

Scan Operators 

Character set membership scan operators apply the sequential membership test of each 

source character to the character set as defined previously. 

SWFD 

SWTD 

 

 

set: I1DD 

 

Top-of-stack 

 


 

for SWFD & SWTD: 

 

source: pntr, opnd Null 

 

 

SWFU 

SWTU 

 

 

set: I1DD 

 

Top-of-stack 

 


 

for SWFU & SWTU: 

 


 

 

6878 7530–007 5–91

Operator Set 

Transfer Operators 

Character set membership transfer operators apply the sequential membership test of 

each source character to the character set as defined previously. Each source character 

that satisfies the membership criterion is transferred to the destination sequence. 

TWFD 

TWTD 

 

 

set: I1DD 

 

Top-of-stack 

 


 

for TWFD & TWTD: 

 


 

 

 


 

 

TWFU 

TWTU 

 

 

set: I1DD 

 

Top-of-stack 

 


 

for TWFU & TWTU: 

 


 

 

 


 

 

5–92 6878 7530–007

Character Translate Operator 

Operator Set 

TRNS sequentially accesses characters from the source sequence, maps each character 

into a specified character set, and stores the translated character into the destination 

sequence. The character set mapping is indicated by a translate table argument. 

TRNS 

 

 

trtab: I1DD 

 

 

 


Top-of-stack 

 



 

 

 


 

 

The translate table must be an IndexedSingleDD, which designates the first word of the 

translate table. Reindex must be enabled in this descriptor. Every word accessed on the 

table must be an operand. Every word accessed in the table must lie within the 

designated virtual segment. 

The translate table is interpreted as an array of words, each containing four right-justified 

8-bit characters; it is indexed by the source character. The selected 8-bit character is 

stored into an EBCDIC destination or the four low- order bits of the character are stored 

into a hex destination. The character is located by the following expression, where Table 

represents the translate table argument and TableSeg represents the segment 

designated by that argument. 

TableSeg[Table.index+WordIndex(c)].[FieldIndex(c):8] 

WordIndex and FieldIndex are computed from the binary representation of the source 

character (c) as follows: 

EBCDIC WordIndex = value of six high-order bits 

FieldIndex = 31 - 8*(value of two low-order bits) 

hex WordIndex = value of two high-order bits 

FieldIndex = 31 - 8*(value of two low order bits) 

TRNS leaves the updated source on top of the stack and the updated destination second 

from top of the stack. 

6878 7530–007 5–93

Operator Set 

Character Sequence Extraction Operator 

SISO extracts a character sequence from the source, creates an operand containing the 

extracted sequence right-justified with leading zero-fill if required, and leaves the 

operand on top of the stack. The length specifies the number of characters in the 

extracted sequence. 

SISO 

 

 


Top-of-stack 

 


source: pntr, opnd opnd(char sequence) 

 

 

The result is a single or double precision-operand depending on the length and the 

source character type. If the source is EBCDIC, the result is single for length less than or 

equal to six and double for {7 to 12}. If the source is hex, the result is single for length 

less than or equal to twelve and double for {13 to 24}. The length must not exceed 12 or 

24 for EBCDIC and hex source, respectively. 

Decimal Character Sequence Operators 

Decimal character sequence operators interpret hex or EBCDIC sequences as digit 

sequences and provide conversion functions among various numeric representations. 

For definitions of digit sequences and decimal sequence operands, see "Decimal 

Sequence Operands" in Section 3. 

The hex representation of a digit sequence is as a hex sequence of the corresponding 

digit values. The EBCDIC representation of a digit sequence is an EBCDIC sequence in 

which the numeric field (low-order four bits) of each character contains a digit value. The 

high-order four bits are called the zone field; zone fields are significant in some 

operators, but they do not form part of the digit sequence. 

A signed decimal integer is represented as a digit sequence and a sign value. Hex "D" 

represents a negative sign; any other 4-bit value represents a positive sign. The sign may 

be placed at either the left (high-order) or right (low- order) end of the sequence. A 

signed sequence of n digits is represented in hex as a sequence of n+1 characters; the 

sign is the leftmost or rightmost character. A signed n-digit sequence is represented in 

EBCDIC as a sequence of n characters; the sign occupies the zone field of the leftmost 

or rightmost character. (Operand digit sequences are always unsigned; EXTF can be 

used to hold the sign.) 

5–94 6878 7530–007

Operator Set 

There are three groups of decimal character sequence pointer operators. The pack 

operators transform a hex or EBCDIC source sequence into a right-justified operand digit 

sequence. The unpack operators transform a left-justified operand digit sequence into a 

hex or EBCDIC destination sequence. The input-convert operators are similar to pack, 

but the integer value of the source sequence is transformed to binary representation. 

ICVD handles a hex source sequence as either unsigned or left-signed, depending upon 

the value of the first character. A nondigit value is considered as a sign; a digit value is a 

digit. The sign is not counted in the length. 

Pack Operators 

Pack operators perform a conversion from the source EBCDIC or hex digit sequence to a 

decimal operand containing the corresponding digit sequence right- justified with leading 

zero-fill. The operand is left as a result on the stack. Nondigits in a hex source sequence 

(other than a sign character) or in the numeric field of an EBCDIC source sequence are 

transferred unmodified to the operand digit sequence. 

The result is a single precision operand if length less than or equal to twelve and double 

precision for {13 to 24}. The length must not exceed 24. 

PKUD 

PKLD 

PKRD 

 

 

Top-of-stack len: opnd(integer) 

 

transformation 

 

for PKxD & PACD: source: pntr, opnd opnd(digit sequence) 

 

 

PKUD leaves EXTF and TFFF in undefined states. All other pack operators set both EXTF 

and TFFF: true = negative sign and non-zero digit sequence, and false = otherwise. If the 

length argument is less than or equal zero, EXTF and TFFF are set false. 

If the length is greater than zero, the source is hex, and there is a sign, the number of 

characters read from the hex sequence is one greater than the length value. A sign is 

always present for PKLD and PKRD and never present for PKUD. If the length is less 

than or equal to zero, no source characters are read and the digit-sequence result is zero. 

6878 7530–007 5–95

Operator Set 

The following are the sign locations for these operators: 

Unpack Operators 

PKUD: none 

PKLD, EBCDIC: zone of leftmost character 

PKLD, hex: leftmost character 

PKRD, EBCDIC: zone of rightmost character 

PKRD, hex: rightmost character 

Unpack operators interpret the source operand as a left-justified digit sequence and store 

the corresponding hex or EBCDIC digit sequence into the destination. Nondigits in the 

operand digit sequence are transferred unmodified to the hex characters or the numeric 

field of the EBCDIC characters in the destination sequence. 

 

 


 

 

Top-of-stack 

source: opnd(digit sequence) 


 

for UPxD & USND: 


 

 

 

 


 

Top-of-stack 

 

transformation source: opnd(digit sequence) source’ 

 

for UPxU & USNU: 

 


 

 

The element_size convention for unpack is that the source operand is unconditionally 

handled as hex. If the destination is a WordDD, it is changed to an EBCDIC CharDD. The 

source must be an operand. The length must not exceed 24. 

5–96 6878 7530–007

Unpack-Unsigned Operators 

Operator Set 

Unpack-unsigned operators store the destination digit sequence without a sign. For an 

EBCDIC destination, the zone field of each character is set to hex "F". For a hex 

destination, the digit sequence is stored with no sign character. 

UPUD 

UPUU 

Unpack-Signed Operators 

Unpack signed operators store the destination digit sequence with a sign; the sign is 

determined by EXTF (external sign flip-flop), where true equals negative and false equals 

positive. The operator mnemonics and names are listed as follows with the location of 

the sign for hex and EBCDIC sequences: 

Hex EBCDIC 

UPLD (unpack left-signed delete) left left zone 

UPLU (unpack left-signed update) left left zone 

UPRD (unpack right-signed delete) right right zone 

UPRU (unpack right-signed update) right right zone 

USND (unpack signed delete) left right zone 

USNU (unpack signed update) left right zone 

Hex "C" and Hex "D" are used as the positive and negative sign characters, respectively. 

For an EBCDIC destination, the sign is inserted into the zone field of the rightmost or 

leftmost character, depending on the operator, and all other zone fields are set to hex "F". 

For a hex destination and length greater than zero, the sign is inserted as the leftmost or 

rightmost character, depending on the operator; length+1 hex characters are transmitted 

to the destination sequence. If the length is less than or equal to zero, no characters are 

transmitted to the destination sequence. 

Unpack operators can be considered short destination operators, analogous to shortsource 

operators. If interrupted at a page boundary, the operator is repeated from the 

beginning after both pages are present. (Although restart mode may be used for 

convenience, it is discarded to force repetition from the beginning.) 

USND and USNU are obsolete, superseded by UPLD/UPRD and UPLU/UPRU. 

6878 7530–007 5–97

Operator Set 

Input Convert Operators 

Input convert operators perform a conversion from the source EBCDIC or hex digit 

sequence to a numeric operand containing the signed integer value of the corresponding 

digit sequence. The operand is left as a result on the stack. TFFF and EXTF are left in 

undefined states. 

The length must not exceed 23. If the length is less than 12, a single_integer is 

produced. If the length exceeds 11, a double_integer is produced. If the length exceeds 

11, but the result absolute value is less than 8**13, some other ClearPath MCP systems 

represent the value as a single_integer or an extended single_integer. 

ICUD 

ICLD 

ICRD 

ICVD 

 

 


 


 

for ICxD & ICVD: source: pntr, opnd opnd(integer) 

 

 

ICVD is deprecated, generally, superseded by ICUD, ICLD, and ICRD; except for certain 

“undefined” situations in COBOL and ALGOL. 

If the length is greater than zero, the source is hex, and there is a sign, the number of 

characters read from a hex sequence is one greater than the length value. A sign is 

always present for ICLD and ICRD and never present for ICUD; a sign is present for ICVx 

when the leftmost hex character is a nondigit. If the length is less than or equal to zero, 

no source characters are read and the binary integer result is positive zero. 

The sign locations for these operators are the same as for the corresponding pack 

operators: 

ICUD: none 

ICLD, EBCDIC: zone of leftmost character 

ICLD, hex: leftmost character 

ICRD, EBCDIC: zone of rightmost character 

ICRD, hex: rightmost character 

ICVD, EBCDIC: zone of rightmost character 

ICVD, hex: leftmost character if nondigit, else none 

5–98 6878 7530–007

Operator Set 

If the source digit sequence contains a nondigit, the result value is undefined, except 

that a sequence of all hex "F" characters is equivalent to a sequence of nines. (Note that 

"digit sequence" does not include the zone fields of an EBCDIC source or a sign character 

in a hex source.) 

Word Transfer Operators 

Word transfer operators transfer word elements from the source to the destination. The 

number of words is specified by the length. The tag of each source word is copied to the 

corresponding destination word. 

A source operand is interpreted as a word or pair of words concatenated with itself 

indefinitely. 

Source and destination IndexedCharDDs, if not already word-aligned, are advanced to 

the next word boundary. 

TWSD 

 

 


 

 

Top-of-stack 



 

for TWSD: 


 

 

TWSU 

 

 


 

Top-of-stack 

 


 

for TWSU: 

 


 

 

6878 7530–007 5–99

Operator Set 

Edit Operators 

Edit mode operators can be considered sub-operators invoked by a special class of 

pointer operators, the enter-edit operators. Most edit operators process source and/or 

destination characters sequentially until a length is exhausted. 

Enter Edit Operators 

There are two modes in which edit operators are executed; each is initiated by an enter 

edit operator. The enter edit operator provides the destination and (except for EXPU) 

source. It may specify update, which causes an updated source (if any) and destination 

argument to be left on top of the stack at termination of edit mode. 

• Table edit mode 

A sequence of edit operators is executed until terminated by ENDE (end edit). Each 

acts on the source and destination supplied by the table enter edit operator; length is 

a parameter for each edit operator requiring it. If update is specified, the updated 

source and destination are left on the stack by ENDE. 

Each edit operator that uses the source/destination updates it internally at 

termination so that a group of edit operators may sequentially process 

source/destination characters. Character-skip operators may advance or back up the 

source/destination to alter the normal sequential processing. 

• Single edit mode 

A single edit operator acts on the source and destination supplied by the enter single 

edit operator. Length is also supplied as a stack argument at entry, whether or not it 

is required by the edit operator. If update is specified, the updated source and 

destination are left on the stack at termination of the edit operator. 

The enter-edit operators validate argument types and perform any needed element_size 

adjustment, as defined previously for other pointer operators. 

With the exception of EXPU, all enter-edit operators set FLTF = 0 when executed in 

initial mode. When restarted, these operators preserve the FLTF value. 

Enter-Table-Edit Operators 

Enter table edit operators supply the source and destination sequences and a reference 

to the sequence, or table, of edit operators to be executed. Each edit operator acts on 

the source and/or destination supplied at entry; length is a parameter for each edit 

operator requiring it. 

5–100 6878 7530–007

Operator Set 

The edit table must be an unpaged IndexedDD, which is interpreted as usual, except that 

the element_size field is ignored and the index field is subdivided as follows: 


esi [38: 3] Edit table syllable index of the first edit operator; 

must be in {0 to 5} 


ewi [32:13] Edit table word index of the word containing the first 

edit operator 

(The set of valid edit-table descriptors includes IndexedSingleDDs and EBCDIC 

IndexedCharDDs that have index or word_index values less than 2**13.) 

The edit table descriptor must be reindex enabled. 

Edit operators (and their parameters) are fetched from the edit table, starting from the 

esi syllable of the ewi word, until completion of an ENDE (end edit) operator. The normal 

code stream is then resumed with the operator following the enter table edit operator. 

Each edit table word that is fetched must have a tag = 0. The table cannot extend 

beyond word index 2**13-1. 

When a table edit sequence is interrupted and resumed, the processor uses restart 

mode with an additional stack argument to provide a progress count. The updated table 

argument points to the edit operator that generated the interrupt. 

TEED 

 

 

edtab: unpaged indexedDD 

 

 

Top-of-stack 



 

for TEED: 


 

 

6878 7530–007 5–101

Operator Set 

TEEU 

 

 

edtab: unpaged indexedDD 

 

Top-of-stack 

 


 

for TEEU: 

 


 

 

 

Enter-Single-Edit Operators 

Enter single edit operators supply the destination sequence, occasionally the source 

sequence, and the length for the edit operator that follows it in the code stream. Each 

argument must be on the stack and must meet type restrictions, although it may not be 

required by the edit operator. 

All edit operators requiring length terminate without transferring any characters if the 

length is zero. 

The enter-single-edit operators cannot introduce the edit operators that insert a character 

conditionally based on FLTF; the excluded operators are INSC and ENDF. The EXSD and 

EXSU operators can introduce the move operators that sense and set FLTF (MFLT and 

MINS), although FLTF is unconditionally reset at the beginning of the operator and 

discarded at the end. 

EXSD 

 

 


 

 

Top-of-stack 



 

for EXSD: 


 

 

 

5–102 6878 7530–007

EXSU 

Operator Set 

 

 


 

Top-of-stack 

 


 

for EXSU: 

 


 

 

 

EXPU 

 

 


 


 

for EXPU: dest: pntr dest’ 

 

 

No source is provided for EXPU; the subsequent edit operator must not require a source. 

(The excluded edit operators are MCHR, MVNU, MINS, MFLT, SFSC, and SRSC.) 

 

The element_size convention applied for EXPU is that a WordDD destination pointer is 

changed to an EBCDIC CharDD. 

No delete form of single pointer enter edit operator is provided. 

Edit Mode Operators 

The following paragraphs define the operators that are executed in edit mode (under the 

control of an enter-edit operator). 

Each edit operator is permitted to update its arguments and enforce all the checking 

associated with pointer update. In particular, any error due to an unrepresentable 

updated pointer can be trapped, even if the resulting pointer would have been deleted 

without further use. 

6878 7530–007 5–103

Operator Set 

Character Skip Operators 

Skip Forward 

Skip Reverse 

Character skip operators advance or reverse the source or destination sequence. Length 

indicates the number of characters to be skipped. 

Length is a parameter for table edit mode only: 

 

 

Operator Skip Skip 

Len 

formats: op op 

 

 

(Table Edit) (Single Edit) 

A skip operation on a pointer alters the pointer so that it designates a different element 

in the same sequence; the length value designates the extent of the change and the 

operator (forward or reverse) its direction. This operation occurs by reindexing the 

pointer. 

The skip operators use aAPIX. The operations must abort when the resulting virtual index 

cannot be represented in an indexed DD; some other ClearPath MCP systems also 

cause them to abort if the resulting pointer designates an element beyond last+1. 

SFSC 

SFDC 

Character skip forward operators advance the source or destination sequence. A source 

operand is circularly rotated left by length characters. A CharDD is incremented by length 

characters. 

The maximum length value that can be applied to a pointer is one that causes the pointer 

to designate the first element beyond the virtual segment. However, software cannot 

count on an error exception for all larger length values. 

The SFSC operator cannot be introduced by EXPU. 

SRSC 

SRDC 

Character skip reverse operators back up the source or destination sequence. A source 

operand is circularly rotated right by length characters. A CharDD is decremented by 

length characters. 

The maximum length value that can be applied to a pointer is one that causes the pointer 

to designate the first element of the virtual segment. 

The SRSC operator cannot be introduced by EXPU. 

5–104 6878 7530–007

Character Insert Operators 

Operator Set 

Character insert operators store a character or a sequence of characters into the 

destination sequence, in some cases conditionally based on the value of FLTF (float 

flip-flop) and EXTF (external sign flip-flop). Each character is a parameter, except for a 

fixed sign character. 

Several insert operators do not allow a hex destination. Those that do store only the 

numeric field of a parameter character. 

INSU 

INSU stores a sequence composed of length repetitions of the parameter character 

(Char) into the destination. 


 

Operator 

 

format: INSU Len Char INSU Char 

 

 


INSC 

INSC stores a sequence composed of length repetitions of a selected parameter 

character into the destination. If FLTF equals zero, ZeroChar is selected; if FLTF equals 

one, NonZeroChar is selected. 

 

 

Operator Zero Non0 

 

format: INSC Len Char Char 

 

 

The INSC operator is defined only for table edit. 

INOP 

INOP stores hex"D" into the zone field of the destination character if EXTF=1; the 

destination character is not altered if EXTF equals zero. Note that in either case the 

destination IndexedCharDD is advanced one character. The destination element_size 

must not be hex. 

6878 7530–007 5–105

Operator Set 

INSG 

INSG stores MinusChar into the destination if EXTF equals one and stores PlusChar if 

EXTF equals zero. The destination element_size must not be hex. MinusChar and 

Pluschar are parameters: 

 

 

Operator Minus Plus 

 

format: INSG Char Char 

 

 

ENDF 

If FLTF equals zero, ENDF stores a selected parameter character into the destination; 

MinusChar is selected if EXTF equals one, and PlusChar is selected if EXTF equals zero. 

If FLTF equals one, no character is stored and the destination IndexedCharDD is not 

advanced. FLTF is unconditionally reset to zero. 

MinusChar and PlusChar are parameters: 

 

 

Operator Minus Plus 

 

format: ENDF Char Char 

 

 

The ENDF operator is defined only for table edit. 

Character Move Operators 

Character Move operators transfer characters from source to destination with editing. 

Some move operators conditionally store into the destination a sequence of repeated 

parameter characters based on the value of FLTF (float flip-flop), the source character, 

and EXTF (external sign flip-flop). 

Move operators cannot be introduced by EXPU. 

If the destination element_size is hex, only the numeric field of a parameter character is 

stored. 

MCHR 

MCHR transfers length characters from the source to the destination. Length is a 

parameter for table edit mode only: 

 

Operator 

MCHR Len MCHR 

format: 

 


5–106 6878 7530–007

MVNU 

Operator Set 

For an EBCDIC source and destination, MVNU transfers length numeric fields from the 

source to the destination, setting each zone field to hex"F". For a hex source and 

destination, MVNU transfers length hex characters (in this case MVNU is identical to 

MCHR). 


 

Operator 

MVNU Len MVNU 

format: 

 


MINS 

MINS performs a leading zero suppression function from the source to the destination 

for length source characters. In the following definition, the source numeric field is the 

numeric field of an EBCDIC character or the entire hex character. 


 

 

Operator Zero Zero 

 

format: MINS Len Char MINS Char 

 

 


While FLTF equals zero and the value of the source numeric field is zero, the ZeroChar 

parameter is transferred to the destination. If the value of the source numeric field is 

nonzero, FLTF is set to one, and the source numeric field is transferred as described in 

the next paragraph. 

When FLTF equals one, the source numeric field is transferred to the destination and the 

zone field of an EBCDIC destination character is set to hex"F". 

MFLT 

MFLT performs a signed leading zero suppression function from the source to the 

destination for length source characters. MFLT is functionally equivalent to MINS (move 

with insert) except for conditional insertion of a sign character into the destination 

sequence. 


 

Operator 

Zero Minus Plus 

format 

MFLT Len Char Char Char 

(Table Edit): 

 

6878 7530–007 5–107

Operator Set 

 

Operator 

Zero Minus Plus 

format 

MFLT Char Char Char 

(Single Edit): 

 

While FLTF equals zero and the value of the source numeric field is zero, the ZeroChar 

parameter is transferred to the destination. 

If FLTF equals zero and the value of the source numeric field is nonzero, the PlusChar (if 

EXTF equals zero) or the MinusChar (if EXTF equals one) is inserted in the destination 

sequence, FLTF is set to one, and the source numeric field is transferred as defined for 

MINS. 

When FLTF equals one, the source numeric field is transferred to the destination, as in 

MINS. 

Note that the number of characters stored into the destination sequence may be 

length+1. Length characters are stored only if FLTF is initially zero and (for length 

characters) all source numeric fields are zero, or if FLTF is initially one. 

Miscellaneous Edit Operators 

RSTF 

RSTF unconditionally resets FLTF (float flip-flop) to zero. 

ENDE 

ENDE terminates table edit mode. The top-of-stack transformation for the TEED or TEEU 

operation is completed. 

ENDE is defined only for table edit. 

Pointer Index Restrictions 

The following information summarizes restrictions that have already been stated or that 

follow from the stated restrictions. 

The 16-bit word_index field in IndexedCharDDs restricts their use to the first 65535 

(2**16-1) words of an actual segment. Operators that generate updated pointers cannot 

update the word index to 65536. For example, TRNS or TUNU cannot access the last 

character of the word at 65535; TWSU cannot access that word at all when the pointer is 

an IndexedCharDD. The delete form of non-edit operators can access all of that word, 

because update does not occur. Software must assume that edit operators have the 

same restrictions as other character update operators, because they may unconditionally 

update. 

A sequence accessed with an IndexedCharDD cannot extend into or beyond the word 

with index 65536 (2**16). 

5–108 6878 7530–007

Operator Set 

With an IndexedWordDD, TWSD and TWSU can access through the word with index 

equals 2**20-1 or 2**20-2, respectively. 

Vector Operators 

A number of operators are provided to perform calculations that are typical of numerical 

(scientific and engineering) computation. 

Vectors and Scalars 

Each vector operator performs an iterative (or sometimes, in principle, parallel) 

computation on a set of elements of one or two virtual segments. Such a set of 

elements is called a vector; it is defined by an IndexedWordDD and a set of index values 

that are applied to it. In most cases the index values are an arithmetic sequence 

j, j + k, j + 2*k, ... 

in which j is the initial index value (supplied via the IndexedWordDD) and k is an integer 

constant called the stride. (Two operators allow the set of index values to be provided 

explicitly in a third vector.) 

Some of the vector computations involve numeric values (operands) that are not in 

vectors; these are called scalars. 

Vector Arguments 

The vectors are named A, B, and (for index sets) I. When no index set is involved, vector 

A is specified by a pair of arguments called vector_A and stride_A. Vector_A is always an 

IndexedWordDD and stride_A is an integer. Vector_B is similarly specified by vector_B 

and stride_B, but in some cases vector_B can be an operand (in which case stride_B is 

not significant but must satisfy type and range restrictions). In two operators, a vector_I 

argument occurs instead of stride_A or stride_B; vector_I has an implicit stride of +1. 

Any IndexedWordDD vector argument must have reindex enabled. The vector_A 

argument must be write-enabled for those operators that store into vector A. 

The notation "B may be scalar" or "B must be vector" is used as shorthand for "vector_B 

must be an IndexedWordDD or operand" or "vector_B must be an IndexedWordDD", 

respectively. 

A[x] denotes the element designated when the initial vector_A argument is reindexed by 

x. Lowercase i denotes an iteration index; A(i) denotes the ith element of vector A, 

counting from 1: A(i) = A[(i-1)*stride_A] normally; and A(i) = A[I(i)] denotes that an index 

set is used. The same notation is used for B, but when vector_B is an operand, B(i) = 

vector_B for all i. 

6878 7530–007 5–109

Operator Set 

Vector Length 

All vector operators accept an argument named length, which specifies the vector length 

(iteration count). The length argument must be a single_integer; it must not exceed 

MaxLen in magnitude. If length is zero or negative, no iterations are performed; 

operators that return results return the corresponding input arguments. 

Strides 

Stride arguments must be single_integers that may be positive or negative but must not 

exceed MaxLen in magnitude. Strides are repeatedly applied as index values to the 

IndexedWordDDs, using common action aAPIX. Note that if stride is +1 and the vector 

argument is an IndexedDoubleDD, successive vector elements differ by two in the word 

index. 

The initial vector descriptor index, the stride, and the length must be such that every 

access to a vector element falls within the designated virtual segment; an error is 

reported only if an out-of-bounds access is attempted. Furthermore, the product of 

stride*(length-1) must not exceed MaxLen for stride_A or stride_B, even when vector_B 

is an operand. 

Vector Access 

Vector elements are fetched and stored using the common actions aFOP and aSOP, 

respectively, with the current vector descriptor. The common action aAPIX is used to 

apply the stride or index-set value to each vector descriptor at each iteration of the 

operator. 

Vector Arithmetic 

The arithmetic performed by vector operators is as defined for the operators ADD, 

SUBT, MULT, MULX, and DIVD. Arithmetic exceptions occur as defined for those 

operators. (No vector operators generate Integer Overflow exceptions.) 

Most vector operators can perform single and double precision computations, depending 

on the types of the arguments. Normal precision rules are applied to individual arithmetic 

operations. The result of addition, subtraction, multiplication, or division is double 

precision if either or both inputs are double; the result is single if both inputs are single. 

However, those operators that perform multiple arithmetic operations (multiply and add) 

in the same iteration are so specified that both operations are in the same precision. 

The term width is defined as the number of words occupied by each vector element or 

scalar. The terms wA and wB denote widths of A and B. It is always required that the 

values to be accumulated or stored be of the same width as the accumulator or vector; 

no implicit type coercion is performed. 

5–110 6878 7530–007

Vector Assignment Operators 

Operator Set 

These operators generate an output vector A by computing each element independently; 

the only vector elements that contribute to the new value of A(i) are A(i) or B(i) or both. 

Vector_A must be write enabled. 

Most operator definitions use succinct notation, in which operations on the vector name 

stand for operations on all the individual elements. 

For example: 

A := A * B 

means 

for i in {1 to length} do A(i) := A(i) * B(i) 

The specific type requirements [scalar or vector; width] are indicated for each operator 

between brackets at the right of the function definitions. 

Dyadic Vector Operators 

These operators act on two vectors. The first five copy a function of B into A; the rest 

replace A by a function of A and B. 

 

 

stride_B 

 

 

 

stride_A 

 

 

Top-of-stack 

length 


 

 

vector_B 

 

 

 

vector_A Null 

 

 

CPV 

A := B [B may be scalar; wB = wA] 

CPVN 

A := - B [B may be scalar; wB = wA] 

6878 7530–007 5–111

Operator Set 

CPVA 

A := abs(B) [B may be scalar; wB = wA] 

CPVS 

A := single (B) [B must be vector; wA = 1] 

Each element of B is converted to single precision, as defined for the SNGL operator. 

CPVD 

A := double (B) [B must be vector; wA = 2] 

Each element of B is converted to double precision, as defined for the XTND operator. 

VPV 

A := A + B [B may be scalar; wB

S 

 

 

 

stride_B 

 

 

 

stride_A 

 

 

Top-of-stack 

length 


 

 

vector_B 

 

 

 

vector_A Null 

 

 

VPS 

A := B + S [B must be vector; wB

Operator Set 

The operation is undefined if I overlaps A. 

SCAT 

for i in {1 to length} do A[I(i)] := B(i) [B may be scalar; wB = wA] 

 

 

stride_B 

 

 

 

vector_I 

 

 

Top-of-stack 

length 


 

 

vector_B 

 

 

 

vector_A Null 

 

 

GATH 

for i in {1 to length} do A(i) := B[I(i)] [B must be vector; wB = wA] 

 

 

vector_I 

 

 

 

stride_A 

 

 

Top-of-stack 

length 


 

 

vector_B 

 

 

 

vector_A Null 

 

 

5–114 6878 7530–007

Reduction Operators 

Linear Sum 

These operators read one or two vectors and produce a scalar result. The vector 

arguments must be IndexedWordDDs; they need not be write enabled. 

These operators sum the elements in a single vector. 

 

 

sum 

 

 

 

stride_A 

 

 

Top-of-stack 

length 


 

 

vector_A sum’ 

 

 

Operator Set 

The sum argument must be an operand with width greater than or equal to wA; the 

arithmetic is performed in double precision if sum is double. 

Quadratic Sum 

SUM 

for i = 1 to length do sum := sum + A(i) 

SUMA 

for i = 1 to length do sum := sum + abs(A(i)) 

These operators compute the inner product of two vectors: 

for i = 1 to length do sum := sum + A(i) * B(i). 

6878 7530–007 5–115

Operator Set 

 

 

sum 

 

 

 

stride_B 

 

 

 

stride_A 

 

 

Top-of-stack 

length 


 

 

vector_B 

 

 

 


 

 

B must be a vector. 

DOT 

The sum argument must be a single precision operand; vector_A and vector_B must be 

IndexedSingleDDs. Multiplication and addition are performed in single precision. 

DOTX 

The sum argument must be a double precision operand. Vector_A and vector_B must be 

IndexedWordDDs; wA and wB are independent. All arithmetic is double precision; 

multiplication is performed as in the MULX operator. 

Recurrence Operators 

Each of these operators iteratively computes a scalar function in which, at each iteration, 

the previous scalar value enters into the computation. The first operator iteratively 

assigns values to the elements of vector A; the others return the final scalar value. 

SEQ 

for i = 1 to length do A(i) := Z := Z + B(i); 

5–116 6878 7530–007

Z 

 

 

 

stride_B 

 

 

 

stride_A 

 

 

Top-of-stack 

length 


 

 

vector_B 

 

 

 

vector_A Null 

 

 

Operator Set 

B may be a scalar or vector; wB must be less than or equal wA. Z must be an operand 

with width equal wA. Vector_A must be write enabled. 

POLY 

for i = 1 to length do Z := A(i) + B(i) * Z 

 

 

Z 

 

 

 

stride_B 

 

 

 

stride_A 

 

 

Top-of-stack 

length 


 

 

vector_B 

 

 

 

vector_A Z’ 

 

 

6878 7530–007 5–117

Operator Set 

B may be a scalar or vector; wB and wA are independent. Z must be an operand with 

width greater than or equal to max(wA,wB); the computation is performed and the result 

returned with the width of Z. 

CHEK 

for i = 1 to length do hash := (hash EQV A(i)).[46:48] 

 

 

hash 

 

 

 

stride_A 

 

 

Top-of-stack 

length 


 

 

vector_A hash’ 

 

 

Vector_A must be an IndexedSingleDD; hash must be a single precision operand. Each 

iteration consists of a one-bit left circular shift of the bit- vector logical equivalence of the 

accumulator and the next vector element. 

SUMW 

for 1 = 1 to length do sum := sum WORDADD A(i) 

 

 

sum 

 

 

 

stride_A 

 

 

Top-of-stack 

length 


 

 


 

 

Vector_A must be an IndexSingleDD; sum must be a double-precision operand. The 

operation is undefined if the initial value in sum is not such that: 

sum.[95:48] + length < 2**48 

5–118 6878 7530–007

Operator Set 

The purpose of the SUMW operator is to provide a means to checksum the vector input 

by adding all its 48-bit integer elements, including the addition overflow, into a 48-bit 

checksum result. Implementations are not required to produce that single precision 

result; therefore, the double precision result need not conform to a specific algorithm. 

However, reduction to a single precision result by performing 48-bit integer addition on 

SUMW's result's two words, adding the overflow, if any, to the single precision result, 

must produce the proper checksum value. 

The implementation of WORDADD is: 

Search Operators 

sum.[95:48] := (sum.[95:48] + sum.[47:48]) + overflow 

sum.[95:48] := (sum.[95:48] + A(i)) + overflow 

sum.[47:48] := 0 

These operators find the virtual index of an extremum (maximum, minimum, or 

maximum absolute value) in a vector. 

 

 

V 

 

 

 

X 

 

 

Top-of-stack 

stride_A 


 

 

length V’ 

 

 

 

vector_A X’ 

 

 

X must be a single precision operand. V must be an operand with width equal to wA. 

The operators iteratively compare the vector elements with V; whenever an element of 

A is more extreme than V, it replaces V and its virtual index replaces X. The final values 

of V and X are left as the results of the operator. 

If the same extreme value occurs more than once in A, the first one encountered is 

reported. If no element in A is more extreme than V, the original arguments V and X are 

unchanged; this is the only case in which the value of argument X is significant. 

Note that the index returned (when changed by the operator) is a virtual index into the 

segment. Thus, if the target array is contained within a larger virtual segment (such as a 

FORTRAN common block), the offset of the array into the segment must be subtracted 

from the operator result to derive an array- relative index. Furthermore, the virtual index 

is defined in words, whether vector_A is an IndexedSingleDD or IndexedDoubleDD. 

6878 7530–007 5–119

Operator Set 

The function VirtualIndex(A(i)) in the following operator definitions is the index (into the 

virtual segment containing A) of the item examined in the ith iteration of the operator. It 

is equivalent to the virtual index that would be reported by the GINX operator applied to 

an IndexedWordDD created by applying the INDX operator to descriptor vector_A with 

index (i-1)*stride_A. 

FMX 

for i = 1 to length do 

if A(i) > V then V,X := A(i),VirtualIndex(A(i)) 

FMN 


if A(i) < V then V,X := A(i),VirtualIndex(A(i)) 

FMXA 


if abs(A(i)) > V then V,X := abs(A(i)),VirtualIndex(A(i)) 

5–120 6878 7530–007

Miscellaneous Operators 

NOOP 

No action is performed. 

PUSH 

Operator Set 

PUSH adds the contents of the expression stack to the topmost activation record, 

leaving a null expression stack. The operation is invalid when a procedure entry code 

sequence is being executed (there is an incipient AR at the top of the stack). 

 

 

expression 

Stack-state 

stack 

transformation: activation 

 

record 

activation 

 

D[LL] record D[LL] 

 

 

NVLD 

An Invalid Operator interrupt is unconditionally generated. 

VARI 

The VARI operator may be considered a primary operator that causes the next code 

syllable to be interpreted as a variant operator. The two operator syllables are tightly 

bound, in that no Asynchronous or External interrupt can occur between the VARI and 

the introduced operator and any RCW that designates a variant operator must point to 

the VARI. 

6878 7530–007 5–121

Operator Set 

Program Restrictions Due to Hidden State 

In addition to visible state, which is accessible directly via various operators, a processor 

maintains other state to facilitate efficient execution. For the most part, such state is 

beyond the scope of the functional specification. However, some restrictions on 

software are necessary to ensure that the processor captured state is consistent with 

the visible state, particularly memory contents. 

For example, a program cannot use a table edit sequence to alter the edit table in use for 

that operation. It is likewise undefined for a translate or set membership operator to 

modify as a destination the table it is using. (However, any store to the table performed 

by the same process prior to the translate or set membership operator must be 

effective.) 

The processor is permitted to capture for each current address couple the contents of 

the word designated for the address couple. If the address designates a reference, the 

processor may capture the contents of the word designated by the reference chain. 

The association remains valid until the addressing environment is changed so as to 

redefine the address couple, unless a synchronizing operator (RDLK) is executed or the 

word is explicitly written via the address couple, an SIRW, or an IndexedDD. (The 

processor is not required to recognize writing via an ASRW.) In addition to single word 

values, the processor can capture a double precision operand: 

• When an address couple directly designates a double precision operand, the 

processor can associate the double operand value with the address couple. The 

processor is not required to recognize modification of the second word; thus the 

following sequence is not permitted: 

VALC lambda, delta 

DUPL 

NAMC lambda, delta+1 

STOD 

VALC lambda, delta (produces undefined result) 

For more information on program restrictions for restricted operators see Section 6. 

5–122 6878 7530–007

Section 6 

Restricted Operators 

The system features and operators described in this section are required by MCP, but 

they are not available to normal user programs. 

Restricted General Operators 

The operators in this group have all been used in earlier systems. In general, they deal 

with requirements common to all ClearPath MCP systems and their successors, 

although in some cases the solutions have required different operators between groups 

of systems. 

Restricted Reference Operators 

These operators are used in all systems controlled by the MCP to access the contents of 

memory in restricted ways. 

RASD 

The restricted operator RASD reads one word of the ASD table. RASD accepts a 27-bit 

integer argument as an ASD_number and a 3-bit integer argument as a word specifier. 

The word accessed is ASDi[ASD_number], where i-1 is the word specifier. 

RASD performs a load-transparent operation, returning the contents of the designated 

ASD-table word. 

 

 

Top-of-stack specifier: sp(integer) 

 


 

ASD_num: sp(integer) any 

 

 

6878 7530–007 6–1


TWOD 

The restricted operator TWOD copies source words into a destination sequence without 

regard to tags. TWOD requires three arguments: a length, source, and destination. 

 

 


 

 

Top-of-stack 

source: pntr, ASRW, opnd 


 

 

dest: pntr, ASRW Null 

 

 

The length must be an integer greater than or equal to zero, or the operation is 

undefined. If the length is zero, no transfer occurs. 

The source must be an operand, an IndexedWordDD, an IndexedCharDD with 

char_index equal to zero, or an ASRW. The sequence defined by an operand is the 

source argument concatenated with itself indefinitely; if the source is a double precision 

operand and the second word is not identical to the first, the result is undefined. The 

destination must be an IndexedWordDD, an IndexedCharDD with char_index equal to 

zero, or an ASRW. A source or destination IndexedDD or ASRW defines a sequence 

consisting of the designated word and its physical successors (the words with the next 

higher memory addresses). The TWOD operand is undefined if the source or destination 

argument is an IndexedDD and the sequence is not entirely within the designated actual 

segment; the following inequality must hold: 

IndexedDD.index + length


WASD overwrites a store object of any type into the designated ASD-table word. 

 

 

specifier: sp(integer) 

 

 

Top-of-stack 

ASD_num: sp(integer) 


 

 

store object: any Null 

 

 

Program Restrictions Due to Hidden State 

The concept of hidden state and some of the restrictions imposed on software are 

introduced in Section 5. Additional restrictions that are imposed on system programming 

are defined here. 

The WASD operator is the only defined mechanism for changing the ASD table. A 

processor may capture the state of an ASD and hold it until that processor performs a 

WASD on that ASD or a move-stack operation. 

In general, software must ensure that no processor could be accessing a segment 

before changing its ASD, except: 

• An ASD marked absent can be changed to one marked present providing that the 

last or only WASD performed to that ASD is the one that changes 

ASD1.present_to_proc from 0 to 1. (Note that ASD1.address can be changed in the 

same WASD.) 

• ASD1.present_to_proc can be changed from 1 to 0 provided that the actual segment 

is not a page table and remains present at the same address; the software must take 

into account the fact that other processors may not be affected by the change until 

they perform a move-stack. (This action is permitted to allow software to determine 

experimentally whether a segment is in frequent use.) Note that this provisional 

resetting of present_to_proc does not establish the ASD as "absent" in the sense of 

the previous list entry; ASD1.present_to_proc can later be changed from 0 back to 1 

without synchronization, but ASD1.address must remain unchanged. 

• The processor can increase ASD2.AS_length for the current stack. 

A processor can capture state from a page descriptor and its ASD between the time a 

copy of the descriptor is brought to the expression stack and the completion of an 

operation that consumes the descriptor. Software cannot safely change a page 

descriptor from touched to untouched or alter the ASD3 for that page if any process is 

accessing that page. 

6878 7530–007 6–3


Branch, enter, exit, and move-stack operators are the only mechanisms for altering the 

sequential execution of the code stream. The result is undefined if the program changes 

a code segment ASD (other than the experimental change of present_to_proc from 1 to 

0 as above) or the contents of the code segment while any processor is executing code 

from the referenced segment. (The processor is free to capture the code-segment base 

address and limit, one or more words of code, and so forth.) 

The effect is undefined of changing the environmental linkage for any activation record 

currently in the addressing environment of a processor. 

The result is undefined of any fetch or store operation in the current stack (whether via 

address couple, SIRW, DD, or absolute address) above the current upper bound for stack 

addressing. That bound is moved upward to the S setting by an explicit PUSH or the 

implicit push of an enter operator; it is moved downward by an exit operator or by a 

DLET operator that moves S below the most recent PUSH setting. 

Restricted Processor State Operators 

These operators are used in prior ClearPath MCP systems and their successors to 

access or modify processor state. All but CHES and IPST are used in all ClearPath MCP 

systems. 

CHES (Libra 6xx and 7xx Systems) 

CHES uses its PCW argument to change the executing processor's active emulation 

code segment. 

 

Top-of-stack 

segment-id: PCW Null 


 

The PCW must reference a present segment whose base address equals zero mod 

2**13, and whose length is not less than 2**13. 

HALT 

The restricted operator HALT is a conditional form of STOP. If the processor Halt 

Boolean is false, HALT is equivalent to NOOP. If the Halt Boolean is true, HALT is 

equivalent to STOP. 

IPST 

IPST returns a 32-bit integer whose bits indicate whether the corresponding processors 

are either halted, initial idle, or not in the partition. The implementation of IPST depends 

on a minimum gap of six milliseconds between executions of IPST from all processors in 

the same partition. 

 

Top-of-stack 

Null 32-bit integer 


 

6–4 6878 7530–007

REXI 

The restricted operator REXI is a synonym for EXIT. 

RPRR 


The restricted operator RPRR requires one 6-bit integer stack argument, which is 

interpreted as a processor register identification (register Id). The result left on top of the 

stack is the value of the specified register. This result value is a k-bit integer, where k is 

the width of the target register. 

 

Top-of-stack 

reg-id: sp(integer) sp(integer) 


 

Readable processor registers are associated with register ids that are a subset of 

integers in the range {0 to 63}; the valid subset, along with the register width, is shown 

in the following table: 

Register ID Register name Width 

LL D[LL] 16 

37 BOSR 0 

38 F 16 

52 S 16 

D[LL] (whose id is LL, the current lex level), F, and S report displacements relative to the 

base of the current stack; BOSR reports 0. The value reported for the S register is the 

displacement of the top-of-stack word after the RPRR argument has been consumed. 

SPRR 

The restricted operator SPRR assigns a value to a register; it requires two stack 

arguments. The second argument must be a 6-bit integer whose value is a valid register 

id. The top argument is the register value; it must be a k-bit integer, where k is the width 

of the destination register. 

 

 

Top-of-stack reg-val: sp(integer) 

 

 

 

transformation: reg-id: sp(integer) Null 

 

 

6878 7530–007 6–5


The contents of the specified register are set to the register value, except when the 

register id is 36 or 42, for which special action is defined later in this description. The 

only defined actual registers are F (id=38) and S (id=52). 

Register id value 36 designates LOSR. SPRR performs a special operation for register id 

36: the register value argument is disregarded (but it nevertheless must be a 16-bit 

integer), and the Stack Overflow detection mechanism is enabled. 

On Libra 6xx and 7xx systems, register id 42 causes the processor to purge its ASD 

cache. The register value is not significant, but must be a 16-bit integer. 

The following table specifies the decimal register id encodings, register names, validity 

for RPRR and SPRR, and register widths (in bits). All register id values not listed are 

invalid. 

Register ID Register name RPRR SPRR Width 

LL D[LL] yes invalid 16 

36 (LOSR) invalid special 

37 (BOSR) yes invalid 0 

38 F yes yes 16 

42 (Purge ASD) invalid special 

52 S yes yes 16 

If the register id designates S, the new register value remains in S at the completion of 

the SPRR operator (the arguments to SPRR are consumed before the register 

assignment is made). 

The invariant S >= F must be preserved in any assignment of a value to S or F. 

STOP 

The restricted operator STOP causes the processor execution to halt in an orderly way 

so that execution can be resumed by an external action. The stack state is unaffected. 

6–6 6878 7530–007

WATI 


The restricted operator WATI leaves on top of the stack a double precision operand 

containing the proc state, except for the proc_id. 

 

Top-of-stack 

Null dp 


 

WATI result: 

First Word Description 

tag Tag = 2 

[47:4] Page Length Indicator (=5) 

[43:28] Reserved 

[15:4] E-mode Level (5=Epsilon) 

[11:4] Features (varies by processor type) 

[7:8] Type 

37=Libra 4000 

43=Libra 680/780/880 

44=Libra 4100 

45=Libra 4200/6200 

Second Word Description 

tag Tag = 2 

[47:12] Emulation code compile Year 

[35:06] Emulation code compile Month 

[29:06] Emulation code compile Day 

[23:08] Emulation code version Mark 

[15:16] Emulation code version Cycle 

WHOI 

The restricted operator WHOI leaves on top of the stack a single_integer containing the 

processor identification number, proc_id. 

 

Top-of-stack 



 

ZIC 

The restricted operator ZIC sets the Interrupt_Count to zero. The stack is unaffected. 

6878 7530–007 6–7


Restricted Task Control Operators 

The operators in this group are used by the MCP to implement task management. All 

Level Epsilon systems, except Libra 4000, support these operators. Libra 4000 systems 

have a Task Control Unit (TCU). The TCU communicates with the processor via system 

messages that provide similar functionality. 

MVST 

MVST changes the processor’s site of activity by deactivating the current stack and 

activating a destination stack. The current code segment and LL are not changed. It is 

assumed that the top activation record, for both the stack being deactivated and the 

stack being reactivated, is entered. 

MVST accepts a 19-bit integer in TOS as the destination stack number. MVST produces 

no result. 

1. Deactivate the current stack: 

The current value of the processor’s Micro Timer register is saved in TOS. That 

register, and any other valid top of stack register (originally below the stack number 

argument), is pushed onto the current stack, causing a Stack Overflow interrupt if 

appropriate. 

A TSCW designating the top activation record is placed in word 0 of the stack. The 

TSCW offset designates the topmost word in that activation, relative to the topmost 

HISW. 

2. Establish the destination stack: 

The ASDAM (ASD Associative Memory) and ACAM (Address Couple Associative 

Memory) are both purged. Any exception to the requirements of establishing the 

destination stack causes a superhalt condition. 

SNR is set from the destination stack number, which is also used as an ASD 

number. The word fetched from ASD1[stack number] must be an ASD1 with 

present_to_proc = 1. The length field in ASD2 defines the length of the stack for 

purposes of Stack Overflow detection. The base word of the stack must be a TSCW, 

which designates the activation record at the top of the stack. The contents of the 

TSCW are distributed to F and S. D[LL] is set to F+1. The general boolean 

accumulators are set to zero. 

The proc id (WHOI) value is stored at the base word of the destination stack. For 

Libra 680/780/880 systems, the top stack word is deleted, and its value is loaded 

into the Micro Timer register, which immediately resumes counting. 

3. Update the display registers and resume code processing: 

Any interrupts during the display update are treated normally. In particular, segments 

referenced by environment links are permitted to be absent. Code processing 

resumes at the operator following the MVST operator. 

 

Top-of-stack 

19-bit integer Null 


 

6–8 6878 7530–007

IDLE 


The restricted operator IDLE loops internally until an Asynchronous or External interrupt 

stimulus is present. At that time, it invokes the interrupt procedure and terminates. The 

CS Boolean is not examined or altered. The interrupt RCW designates the operator 

following the IDLE. There is no net effect on the stack state from IDLE, the interrupt, 

and resumption of the code stream. 

PAUS 

The restricted operator PAUS loops internally until an Asynchronous or External interrupt 

stimulus is present, at which time the operator terminates normally. The stack is 

unaffected. 

The PAUS and IDLE operators differ in that the IDLE operator causes the interrupt to 

occur, regardless of control state. The interrupt occurs immediately after a PAUS if the 

CS Boolean if false or the interrupt is not masked by the CS Boolean; otherwise, the 

interrupt remains pending. 

RIPS 

The restricted operator RIPS returns the value of specific processor state. RIPS requires 

one single precision integer state identifier argument. RIPS produces a word result. 

For Libra 680 and 690, the only valid state identifier equals 7, which specifies the interval 

timer granularity as a fraction of 512 microseconds. 

 

Top-of-stack 

state identifier: sp(integer) word 


 

RUNI 

RUNI sets the Run Timer of the executing processor to 30 seconds. RUNI accepts no 

arguments and produces no result. Software is required to reset the Run Timer before it 

decrements to zero; otherwise, a Run Timer interrupt is generated. 

SINT 

SINT arms and sets the Interval Timer for the executing IP. SINT accepts a positive sp 

operand less than 2**11 in TOS (timer value) and produces no result. The time interval is 

the product of the timer value multiplied by 512 microseconds. The timer’s granularity is 

reported by the RIPS operator. When an Interval Timer expires, the IP generates an 

Interval Timer interrupt. 

 

Top-of-stack 

sp operand Null 


 

6878 7530–007 6–9


Restricted Time of Day Operators 

Real Time of Day: 

1. The RTOD value supports a software algorithm to determine time in the normal 

sense. 

2. It must be loaded at least once a day by the WTOD operator. 

3. Its value is available to all current ClearPath MCP systems via the RTOD operator. 

Machine Time of Day: 

1. The MTOD value supports a software algorithm to determine time since the last 

halt-load. 

2. It must be cleared at least once a day by the RCMT operator. 

3. Its value is available only to a subset of ClearPath MCP systems. 

RCMT 

RDMT 

The restricted operators RCMT and RDMT leave on top of the stack a 36-bit integer 

containing the value of the machine time of day clock. The range of values is 

{0 to 2**36-1} in units of 2.4 microseconds. 

Following the above, RCMT clears the machine time of day clock. 

 

Top-of-stack 



 

RTOD (see Section 5) 

WTOD 

The restricted operator WTOD sets the real time of day clock from an operand on top of 

the stack. The argument must be a 36-bit integer. 

 

Top-of-stack 

time: sp(integer) Null 


 

6–10 6878 7530–007

Restricted Platform Operators 


The restricted platform operators apply to Libra 6xx and 7xx systems only. The operators 

in this group deal with requirements that are unique to functioning on an Intel compatible 

platform. 

Restricted Memory Access Functions 

This subsection defines the various types of logical memory and describes how the Emode 

environment accesses each type. 

Platform Memory 

Coherent memory refers to any logical memory space that is mapped to MSU physical 

memory. Prior to the CMP platform, this was the only type of logical memory. 

E-mode memory refers to two coherent memory regions used exclusively as the E-mode 

address space. The region containing address 0 is known as low E-mode memory. The 

second region is known as high E-mode memory. These regions can be disjoint in terms 

of logical addresses. Each word is treated as a 56-bit word; the extra 8-bits supplied by 

the platform are ignored. 

Byte memory refers to a coherent memory region whose address range is typically 

above high E-mode memory. Each 64-bit word is generally viewed as two 32-bit 

elements. 

Non-coherent byte memory refers to two memory regions that are outside of coherent 

memory space, typically PCI local memory mapped to a logical address range that does 

not overlap with any coherent memory range. The region containing the lower address 

range is known as low NCB memory. The region containing the higher address range is 

known as high NCB memory. Each 64-bit word is generally viewed as two 32-bit 

elements. 

Non-coherent I/O space refers to an address space within PCI local memory that is 

completely separate from the set of addresses used by the other memory areas. PCI 

devices often use this I/O space to provide host access to 32-bit hardware registers. 

External memory refers to any memory region outside the E-mode address space that is 

accessed as 32-bit data. External memory includes byte memory, non-coherent byte 

memory, and non-coherent I/O space. The IP accesses external memory via 32-bit 

system operators that are defined in the following paragraphs. 

6878 7530–007 6–11


ASD Segment Types 

The Segment Type field in ASD1 ([47:2]) is used to identify the type of memory being 

referenced. On previous systems, when software allocates an ASD, it unconditionally 

sets the segment type to 1, which indicates the address in ASD1 references E-mode 

memory. To distinguish the new logical memory types, two additional segment types are 

defined. 

External Memory Access 

Segment Type Definition 

0 Unused 

1 Byte or E-mode Memory 

2 Non-coherent Byte Memory 

3 Non-coherent I/O Space 

External memory is viewed as 32-bit elements accessed through a word reference 

operation. The ASD segment type of a source descriptor (for a read) or destination 

descriptor (for a write) determines the type of external memory to access. 

The word reference operation reads or writes a 32-bit element. The read operation reads 

a 32-bit element from an external memory address aligned on a 4-byte boundary and 

returns a 32-bit integer result to the top of stack. There may be state changes associated 

with reading non-coherent memory. The write operation writes a 32-bit element to an 

external memory address aligned on a 4-byte boundary. 

Depending on whether a read or write operation is performed, the system operators that 

access external memory require a source or destination index, based on a 32-bit element 

size. An index with an even value refers to the lower 4 bytes of a 64-bit word. An index 

with an odd value refers to the upper 4 bytes of a 64-bit word. 

When writing to external memory, software may optionally provide a Byte Disable mask 

in [47:4] of each data word to control which of the 4 bytes is written. The transfer and 

word reference operations both support the Byte Disable mask. The following table 

defines the corresponding data byte for each bit in the Byte Disable mask. 

Byte Disable Mask Data Byte 

[47:1] [31:8] 

[46:1] [23:8] 

[45:1] [15:8] 

[44:1] [07:8] 

The word address range for non-coherent I/O space is 8K words (0 to 1FFF). This allows 

access to 16K 32-bit elements. Software typically accesses this data via a word 

reference operation rather than a transfer operation, but this is not enforced. 

6–12 6878 7530–007


When software allocates a descriptor to external memory, software must restrict its use 

to the 32-bit operations defined for external memory. External memory descriptors must 

be unindexed and single precision. The descriptor’s ASD must specify an address and 

length in terms of 64-bit words. 

Partitioning of Logical Memory 

The following diagram illustrates how IP range registers are used to partition logical 

memory. 

High NCB Memory Limit → 

High NCB Memory Base → 

Byte Memory Limit → 

Byte Memory Base → 

High E-Mode Memory Limit → 

High E-Mode Memory Base → 

Low NCB Memory Limit → 

Low NCB Memory Base → 

Low E-Mode Memory Limit → 

Low E-Mode Memory Base (0) → 

Logical 

Memory Area 

Non-coherent 

Byte Memory 

Byte 

Memory 

High E-Mode 

Memory 

Non-coherent 

Byte Memory 

Low E-mode 

Memory 

ASD 

Seg 

Type 

Memory 

Region 

Type 

Operator 

Class 

Coherent 

Non-coherent I/O space (segment type 3) is omitted from the diagram to emphasize the 

unique set of logical addresses among the other memory types. 

6878 7530–007 6–13 

2 

1 

2 

1 

PCI Hole 

(Upper) 

Exclusive 

(Upper) 

PCI Hole 

(Lower) 

Exclusive 

(Lower) 

32-Bit No 

32-Bit Yes 

E-Mode Yes 

32-Bit No 

E-Mode 

Yes


Invalid Address Detection 

Initialization and software maintain several pairs of 20-bit range registers to facilitate 

invalid address detection. The value of each base and limit pair is configuration 

dependent. 

Each register value represents a word address within a 36-bit limit. Thus, range registers 

are compared to [35:20] of a given 36-bit logical word address. A register width of 20 bits 

implies a minimum increment of 64K words for each logical memory type, except noncoherent 

I/O space. 

For standard E-mode operators accessing data through a normal ASD (segment type = 

1), the address must be within either the Low E-mode Memory range or the High Emode 

Memory range. 

For 32-bit access operators accessing data through a normal ASD (segment type = 1), 

the address must be within the Byte Memory range. 

For 32-bit access operators accessing data through a non-coherent byte ASD (segment 

type = 2), the address must be within either the Low NCB Memory range or the High 

NCB Memory range. 

For 32-bit access operators accessing data through a non-coherent I/O space ASD 

(segment type = 3), the address must be less than 8K. 

In addition, an Invalid Address interrupt is reported when standard E-mode operators 

attempt to access data through ASD segment types 2 and 3 (non-coherent memory), and 

when any operator attempts to access data through ASD segment type 0. 

When the IP reports an Invalid Address interrupt, the P2 parameter is a proper reference 

(ASRW, SIRW, or IDD) to the address in question. The P2 reference, ASD segment type, 

and range register values, determine the type of memory operation that caused the 

interrupt. 

Restricted Memory Access Operators 

REMW (Libra 6xx and 7xx Systems) 

REMW accepts an unindexed copy descriptor in TOS2 (source descriptor referencing 

coherent or non-coherent byte memory) and an integer in TOS (source index based on a 

32-bit element size). REMW returns the referenced 32-bit element as an integer result. 

 

 

Top-of-stack Source index 

 


 

Source UDD 32-bit integer 

 

 

6–14 6878 7530–007


WEMW (Libra 6xx and 7xx Systems) 

WEMW transfers 1, 2 or 4 bytes of a 32-bit element from an E-mode memory word to 

an external memory word. WEMW accepts an unindexed copy descriptor in TOS3 

(destination descriptor referencing coherent or non-coherent byte memory), an integer in 

TOS2 (destination index based on a 32-bit element size), and a 48-bit operand in TOS 

(byte disable mask in [47:4] and 4 bytes of data in [31:32]). WEMW produces no result. 

 

 

Data operand 

 

 

Top-of-stack 

Destination index 


 

 

Destination UDD Null 

 

 

Restricted System Interrupt Functions 

The interrupt structure of the CMP platform is based on the INTEL Streamlined 

Advanced Programmable Interrupt Controller (SAPIC) architecture. Any reference to 

APIC in this document implies SAPIC. 

APIC Description 

There are two forms of APIC units: Local and I/O. There is one Local APIC per processor 

and one I/O APIC for each grouping of PCI agents. Each Local APIC is able to send 

interrupts, accept interrupts, and distribute interrupts to a processor. Each I/O APIC is 

able to process interrupt requests from a PCI agent and route the interrupt requests to a 

Local APIC. 

There are three interrupt command types defined for an MCP partition. An Inter- 

Processor Interrupt (IPI) refers to a processor-to-processor interrupt request. An I/O 

interrupt refers to an I/O APIC to processor interrupt request. An External Task Priority 

(XTP) request enables a processor to change its XTP register in the platform. XTP values 

are used by the platform to select the destination of a redirectable I/O interrupt. 

Most IPI and I/O interrupt requests generate an interrupt to software. An XTP request 

does not. 

Interrupt Vectors 

IPI and I/O interrupt requests specify an interrupt vector (not to be confused with the Emode 

Interrupt Vector at ASD3), a decimal integer between 0 and 255. Each interrupt 

vector represents an interrupt source or action. The higher the vector, the higher the 

interrupt priority. Each IPI and I/O interrupt request received by a particular processor 

causes it to set the corresponding bit in its Interrupt Request Register (IRR). See 

“Maskable External Interrupts” above for assignments. 

6878 7530–007 6–15


Interrupt Routing 

IPI and I/O interrupt requests specify an IP destination and a delivery mode that 

determines how the interrupt is routed. 

An interrupt request with a fixed delivery mode is routed to the processor specified in 

the destination field. The destination field, or DEST ID, identifies the IP. IPI and I/O 

interrupt requests will normally specify fixed delivery mode. 

An interrupt request with a redirectable delivery mode is routed to the processor having 

the lowest XTP value. XTP values range from 0 to 4’F’. 

An IPI that specifies a start up delivery mode is valid only for an IP in an Initial Idle or 

Recovery Idle state. 

An IPI that specifies a non-maskable delivery mode is reported to software regardless of 

control state. 

Local APIC Registers 

Each Local APIC contains several registers that are used to manage and process 

interrupts. This section describes the registers that can be accessed by software via the 

Read Register (RREG) and Write Register (WREG) operators. 

Interrupt Request Register (IRR) [read only, 256 bits] 

255 15 

Interrupt Request Bits Not Used 

The IRR contains active interrupt requests that have been accepted by the Local APIC. 

An active interrupt is represented by bit n being set, where n is a vector between 16 and 

255. Interrupt request bits 0 through 15 are reserved. An interrupt to system software 

occurs when one or more request bits are set. If more than one interrupt is active at the 

same time, the most significant bit is reported first. The processor resets an IRR bit 

when it reports the corresponding interrupt to software. The IRR is implemented as 

eight 32-bit registers, IRR0 through IRR7. Interrupt request bit n is located in IRR (n DIV 

32), at bit position (n MOD 32). 

Interrupt Mask Register (IMR) [write only, 256 bits] 

255 15 

Interrupt Mask Bits Not Used 

The IMR is used to mask interrupts normally reported by the IRR. Each IMR bit 

corresponds to an IRR bit. A value of 0 enables an interrupt, and a value of 1 disables an 

interrupt. The Local APIC does not set an IRR bit if the corresponding bit is set in the 

IMR, and setting an IMR bit resets the corresponding IRR bit. The IMR is implemented 

as eight 32-bit registers: IMR0 through IMR7. Interrupt mask bit n is located in IMR (n 

DIV 32), at bit position (n MOD 32). All interrupt request bits are disabled during a start 

sequence. 

6–16 6878 7530–007

Local ID Register (LID) [read only, 16 bits] 

15 7 

Dest ID EID 


The LID determines whether the Local APIC will accept an interrupt request. A Local 

APIC accepts an interrupt if the specified destination matches the destination in the LID. 

Software has no direct use for this register. 

Interrupt Command Register (ICR) [write only, 32 bits] 

31 29 23 15 07 

1’01’ Mode Flags Vector Dest ID EID 

1’11’ 0 XTP 

The ICR is used to send either an IPI or XTP request. The type field in [31:2] is set to 1 

for an IPI and 3 for an XTP request. Writing the ICR generates a bus transaction that is 

recognized by the platform. Fields within the ICR are defined as follows: 

IPI Mode Flag Format 

[29:1] = Destination Mode 

0 = Physical 

1 = Logical 

[28:3] = Delivery Mode 

0 = Fixed 

4 = NMI 

6 = Start up 

[25:1] = Trigger Mode (=0) 

0 = Edge (no EOI expected) 

[24:1] = Not used (=0) 

Destination ID (Dest ID) 

[15:4] = Cell 

[11:1] = 0 

[10:2] = ASIC socket 

[08:1] = Core within socket 

Inter-Processor Interrupts 

A processor can interrupt another processor by sending it an Inter-Processor Interrupt 

(IPI). Software initiates an IPI request by directing a processor to write the Interrupt 

Command Register (ICR), which in turn generates a platform transaction. A processor 

writes the ICR by executing a Write APIC Register (WREG) operator. 

The Local APIC recognizes three IPI requests: 

• Maskable Interrupt 

• Non-maskable Interrupt 

• Startup 

6878 7530–007 6–17


Maskable Interrupt requests are implemented via high priority interrupt vectors in the 

IRR. Non-maskable Interrupt and Startup requests are implemented via high priority 

delivery modes that override other pending interrupts. The following table summarizes 

the delivery and response for each IPI request: 

IPI Request Delivery Destination Response 

Maskable Interrupt High priority vector MEI 

Non-maskable Interrupt IPI delivery mode ROI 

Startup IPI delivery mode Moved to spec’d stack 

Maskable Interrupt Request 

The Maskable Interrupt request is used to interrupt a processor in the partition, typically 

for a higher priority stack or function. In response to this request, the destination IP 

reports a Maskable MEI to software. This interrupt is masked by control state. 

To issue this request, the following values are set in the ICR: 

• Message Type = 1 (IPI) 

• Delivery Mode = 0 (fixed) 

• Trigger Mode = 0 (edge) 

• Vector = 4’D9’ (maskable interrupt) 

• Destination = 

Non-maskable Interrupt Request 

The Non-maskable Interrupt request is used to interrupt a processor out of control state, 

presumably because it failed to respond to a Maskable Interrupt. In response to this 

request, a processor reports a Non-maskable Interrupt to software. 



• Delivery Mode = 4 (NMI) 


• Vector = 


Startup Request 

The Startup request moves a processor from an initial idle state to a specified stack. It is 

intended for primitive software environments and IP reconfiguration. Prior to sending the 

request, software must prepare the stack with proper stack linkage and any required 

activation records. The destination IP interprets the 8-bit vector in the ICR as a stack 

number. Therefore, the Startup request is valid for stacks 1 to 255. No interrupt is 

reported to software. 

6–18 6878 7530–007


Both Server Control and software can transition a processor to an initial idle state. A 

processor in this state only responds to a Startup IPI. 

In response to a Startup IPI or Start request from Server Control, the destination 

processor performs the “establish destination stack” part of a MVST operator, except 

that there is no word to load into the Micro Timer. F must point to the topmost HISW 

and S must point to the topmost RCW. The IP requires an initial LL of 1 in the topmost 

RCW. Then the processor exits as defined by that RCW and HISW. 



• Delivery Mode = 6 (start up) 


• Vector = 


Restricted System Interrupt Operators 

EXTB (Libra 6xx and 7xx Systems) 

EXTB cuts the stack back to D[LL]+1, pushes onto the stack an integer equal to the most 

significant interrupt request in the IRR, and dynamically branches to an MEI procedure 

whose PCW resides at a fixed D[0] offset known to the processor. 

EXTB accepts no arguments and produces no result. The IRR bit corresponding to the 

interrupt request is reset. 

EXTB executes at the same stack history and lexical level that results from a MEI. 

Software must maintain control state upon branching to the target procedure, as the IP 

requires that EEXI never follow EXTB in the code stream. 

RIRR 

RIRR returns an 8-bit integer between 0 and 255 that corresponds to the most significant 

bit set in the Interrupt Request Register (IRR). RIRR accepts no arguments. If no bits are 

set in the IRR, RIRR returns -1. 

 

Top-of-stack 

Null integer 


 

6878 7530–007 6–19


RREG (Libra 6xx and 7xx Systems) 

RREG reads a specified Local APIC register and returns a 32-bit integer result. RREG 

accepts an 8-bit integer argument in TOS (register ID). 

 

Top-of-stack 

Register ID 32-bit integer 


 

WREG (Libra 6xx and 7xx Systems) 

WREG writes a specified Local APIC register. WREG accepts an 8-bit integer argument 

in TOS (register ID) and a 32-bit integer argument in TOS2 (register data). WREG 

produces no result. 

 

 

Top-of-stack Register ID 

 

 

 

transformation: Register data Null 

 

 

Both the IRR and IMR are implemented as eight 32-bit registers. Note that the IRR is 

read-only. Software cannot use WREG to write the IRR. 

Register names and their IDs appear below. RREG and WREG produce unknown results 

if their register ID argument is not in the table. 

Register Name Register ID Read/Write 

Interrupt Request Register 0 4’00’ R 








Interrupt Mask Register 0 4’08’ W 

Interrupt Mask Register 1 4’09’ W 

Interrupt Mask Register 2 4’0A’ W 

Interrupt Mask Register 3 4’0B’ W 

Interrupt Mask Register 4 4’0C’ W 

6–20 6878 7530–007

Register Name Register ID Read/Write 

Interrupt Mask Register 5 4’0D’ W 

Interrupt Mask Register 6 4’0E’ W 

Interrupt Mask Register 7 4’0F’ W 

Interrupt Command Register 4’10’ W 

Local ID Register 4’11’ R 


Restricted Time of Day Functions (Libra 6xx and 7xx Systems) 

Each processor has a TOD counter to support Real Time of Day (RTOD) and Machine 

Time of Day (MTOD). TOD counters increment at a rate that is a function of the system 

bus clock. 

Time of day counters are synchronized, which allows each processor to access its own 

counter. At any point in time, each processor will generate the same RTOD result and 

the same MTOD result. Synchronization of the counters is driven by software. 

Two scratch pad locations are used to implement time of day. One is an RTOD base 

value and the other is an MTOD base value. All processors in a system share these two 

base values. 

Real Time of Day 

To initialize RTOD during a start sequence, Server Control clears the RTOD counter in 

the BSP (Boot Strap Processor) and writes the partition time to a reserved memory 

location. Software initializes the RTOD base by executing WIPS with a state identifier 

equal to Set RTOD Base and a state value equal to the time base provided by Server 

Control, converted to 2.4 microsecond units. This case of WIPS sets the RTOD base to 

an equivalent value based on the interval of the system clock. Since this interval can 

vary, Server Control does not set the RTOD base directly. 

To calculate an RTOD value, the processor adds its TOD counter to the RTOD base and 

converts the result to an equivalent value based on a clock with a 2.4-microsecond 

interval. The RTOD operator returns this value as a 36-bit integer. Software cannot 

execute the RTOD operator until the RTOD base has been set via WIPS. 

The Write Time of Day (WTOD) operator effectively sets the RTOD base to the new time 

of day value minus the TOD counter of the executing processor. Software continues to 

provide the WTOD argument in 2.4-microsecond units. In a multiprocessor configuration, 

other processors cannot execute RTOD while the master processor executes WTOD. 

WTOD does not generate an Unimplemented Operator interrupt as it did on some 

previous platforms. 

The RTOD counter continues to increment when an IP halts. 

6878 7530–007 6–21


Machine Time of Day 

To initialize MTOD during a start sequence, Server Control sets the MTOD base to zero 

and clears the TOD counter in the BSP. 

To calculate an MTOD value, the processor adds its TOD counter to the MTOD base and 

converts the result to an equivalent value based on a clock with a 2.4 microsecond 

interval. The Read MTOD (RDMT) operator returns this value as a 36-bit integer. 

Software maintains a machine running time value that is the sum of MTOD and a global 

memory cell, MTIMEBASE. To prevent overflow of the 36-bit MTOD result, software 

periodically adds MTOD to MTIMEBASE and clears the MTOD result via the Read and 

Clear MTOD (RCMT) operator. RCMT returns a 36-bit MTOD result, like RDMT, but it 

also sets the MTOD base to zero minus the TOD counter, which effectively clears the 

MTOD result. 

Since Server Control is not involved in a programmatic load (PHL or CM), software must 

execute RCMT during system initialization in order to clear the machine running time 

(MTIMEBASE + MTOD). In this case, the RCMT result is discarded. 

Synchronization 

Software initiates synchronization of the TOD counters during initialization and during IP 

reconfiguration. During initialization, synchronization is required only for an Server Control 

Start; it is not required for a programmatic start (PHL and CM), as the counters are 

already synchronized in this case. 

The synchronization action affects any IP owned by the partition. During initialization, 

software only needs to initiate synchronization once (before the BSP starts any other IP). 

During dynamic reconfiguration, synchronization must occur for any IP whose TOD 

counter has not been synchronized by the current partition. In the reconfiguration case, 

software must first select a master IP and quiet other running processors via DIAL and 

ANSWER. 

Synchronization requires participation by Server Control. The overall sequence follows: 

1. BSP (or master IP) sends an MCP to Server Control Synchronize Time message. 

2. BSP (or master IP) executes WIPS with a Synchronize TOD state identifier. 

3. Server Control triggers the time of day synchronization signal. 

4. Server Control acknowledges the MCP to Server Control message. 

The Synchronize TOD case of WIPS does the following: 

1. Disables the loop timer. 

2. Sets the processor’s light to Wait TOD Sync. 

3. Saves the MTOD result (MTOD base plus TOD counter). 

4. Enters a loop that continually reads the TOD counter until the synchronization signal 

clears it. 

5. Sets the processor’s light back to Running. 

6–22 6878 7530–007

6. Adds the last saved TOD counter to the RTOD base. 

7. Sets the MTOD base to the saved MTOD result. 


Software provides the BSP (or master IP) unit number in the MCP to Server Control 

Synchronize Time message. Server Control must verify that the status light of that IP is 

Wait TOD Sync before it triggers the synchronization signal. 

The TOD counters are synchronized when WIPS completes execution. Note that the 

MTOD result is frozen (does not advance) during execution of this WIPS case. 

Time Management (Libra 4000 System) 

The Timer Module is a firmware operating environment application that provides time 

management services to the firmware. The Timer Module manages the following timing 

functions. 

• Real Time of Day (RTOD) 

• Machine Time of Day (MTOD) 

• Interval Timer 

• Run Timer 

• Loop Timer 

• Micro Timer 

• Performance Tuning 

The Timer Module supports interfaces to read and set these E-mode timers. The Timer 

Module is responsible for converting the timer resolution and format available on the 

host platform to the apparent resolution and format expected by the firmware. Except 

for the Micro Timer, the E-mode format is generally an integer with an apparent 

resolution of 2.4 microseconds. The Timer Module ensures access to monotonically 

increasing timer values. This is a critical requirement for MCP software. 

Another purpose of the Timer Module is to have a central and coherent repository for 

timing functions. This ensures that all functions requesting time values obtain them from 

the same source. As a result, there is no drift or inconsistency in the returned values. In 

addition, the Timer Module enables timing functions to be independent of the hardware 

platform. 

Time of Day Requirements 

MCP software places the following requirements on RTOD and MTOD: 

• The time of day result must have a 2.4-microsecond granularity. 

• At any point in time all processors must produce the same time-of-day result. 

The time-of-day result cannot decrease between any two read operations. 

Real Time of Day (RTOD) 

RTOD is a 36-bit counter that increments continuously, even when the MCP partition is 

stopped. RTOD reflects a 24-hour clock time. 

6878 7530–007 6–23


The Read Time of Day (RTOD) operator returns this value as a 36-bit integer with an 

apparent resolution of 2.4-microseconds. 

The Write Time of Day (WTOD) operator sets the RTOD register. The argument to 

WTOD is a 36-bit integer in 2.4 microsecond units. In a multiprocessor configuration, the 

MCP must ensure that processors do not execute RTOD and WTOD at the same time. 

WTOD does not change the firmware operating environment time of day. 

WTOD is a fully implemented operator. On hard IP systems that support XFNC 

messages, WTOD generates an Unimplemented Operator interrupt and, in response, the 

MCP directs a message to the IOU. 

Machine Time of Day (MTOD) 

MTOD is a 36-bit counter that increments continuously while the MCP partition is 

running. MTOD stops incrementing when a partition halts and resumes incrementing 

when a partition continues. MTOD is initialized to 0 only when System Control starts a 

partition. MCP software cannot write MTOD. 

MCP software requires MTOD to initiate I/O requests, and IOM units require MTOD to 

time I/O operations. MTOD is useful in these cases because I/O finish time is 

guaranteed to be greater than I/O start time, even across midnight when RTOD is reset. 

MCP software reads MTOD by an XFNC message to the MIU. The MIU destination 

dates back to hard IOM systems. The soft IOM does not support an MIU function; 

however, IOM firmware knows how to route this message. The MTOD result is a 36-bit 

integer with an apparent resolution of 2.4 microseconds. 

MCP software maintains two global memory cells, MOFFSET and MTIMEBASE. These 

values are functions of MTOD and are used to handle wraparound of the 36-bit MTOD 

result. CLOCK is the MCP interface that returns machine running time. For TCU 

machines, CLOCK returns 

(((MTOD & 1 [36:1]) - MOFFSET).[35:36] + MTIMEBASE) 

On a programmatic halt/load, the MCP clears MTIMEBASE and sets MOFFSET to 

MTOD. This effectively “resets” CLOCK. 

Interval Timer 

The Interval Timer is set by MCP software by an XSUB message to the TCU. The Interval 

Timer has an apparent resolution of 2.4 microseconds and indicates the length of time a 

processor can execute on a stack when there are no higher priority stacks. The TCU 

maintains one Interval Timer per processor. When an Interval Timer decrements to 0, an 

Interval Timer interrupt is reported to the TCU, which might optionally reschedule the 

processor. 

6–24 6878 7530–007

Run Timer 


The Run Timer is a partition-wide value reset periodically by MCP software by an XFNC 

message to the TCU. By convention, MCP software specifies a default setting of 30 

seconds. If the timer decrements to zero before being reset or disabled, a Run Timer 

interrupt is reported to the TCU, which then initiates a stop partition request to System 

Control. 

Loop Timer 

The Loop Timer is reset by the CPM at the start of each instruction and sometimes 

periodically during execution of “long” operators. If the Loop Timer reaches a value of 20 

seconds before being reset or disabled, the CPM reports a Loop Timer interrupt to the 

MCP. 

Micro Timer 

The Micro Timer is a counter that enables performance modeling software to measure 

code execution time with a finer granularity than the 2.4-microsecond interval of RTOD 

and MTOD. 

The CPM implements a 48-bit Micro Timer for each executable stack. The Micro Timer 

value for a given stack only accumulates when a CPM is on that stack. The initial Micro 

Timer value is zero. 

When a CPM moves off a stack, it saves the current Micro Timer value in internal stack 

state. When a CPM moves onto a stack, the saved Micro Timer value resumes 

incrementing from its previous value. 

Unlike the Micro Timer implementation for hard processors, the CPM provides this 

feature with no dependency on MCP software, such as the need to provide an extra cell 

on each new stack. 

The Read Micro Timer (RMTR) and Write Micro Timer (WMTR) operators provide access 

to the Micro Timer value for the current stack (SNR). MCP software cannot access the 

Micro Timer value of an inactive stack. 

Performance Tuning 

The Timer Module supports performance tuning functions. The Timer Module can 

change the performance of the CPM to calibrate system performance and to avoid 

starvation of other processes. Performance tuning allows the CPM to run at a specified 

percentage of its potential performance. The Timer Module provides an interface to the 

CPM for this feature. The WATI result optionally reports a value (PL) that maps to this 

specified percentage. 

6878 7530–007 6–25


System-Specific Platform Support Operator 

WIPS is defined by various ClearPath MCP systems as required by the system features 

of each. 

WIPS 

WIPS assigns a state value to a specific processor state. WIPS accepts an integer in 

TOS2 (state value) and an integer in TOS (state identifier). WIPS produces no result. 

 

 

Top-of-stack State identifier 

 

 

 

transformation: State value Null 

 

 

Libra 6xx and 7xx Systems 

WIPS State 

Identifier 

Value 

Description 

Set RTOD Base 4’4’ Converts the state value argument to a value based on the 

interval of the system clock and uses the result to set the 

RTOD base word in the scratch pad. 

Synchronize TOD 4’5’ Sets the IP light value to Wait TOD Sync, saves the MTOD 

result, and loops reading RTOD until the counter is cleared by a 

synchronization signal triggered by Server Control. The state 

value argument is ignored. 

Move Idle 4’6’ Moves the IP off the current stack to an Initial Idle state 

regardless of control state. The TSCW for SNR is updated as if 

a MVST operator executed. The state value argument is 

ignored. This WIPS case must execute at LL=1. 

Continue 

Notification 

Low E-mode 

Memory Limit 

High E-mode 

Memory Base 

High E-mode 

Memory Limit 

Low NCB Memory 

Base 

Low NCB Memory 

Limit 

High NCB Memory 

Base 

4’7’ Indicates the IP has reported an interrupt after being continued 

from a halted state. The state value argument is ignored. 

4’15’ Sets the Low E-mode Memory Limit register to [35:20] of the 

state value argument. 

4’16’ Sets the High E-mode Memory Base register to [35:20] of the 


4’17’ Sets the High E-mode Memory Limit register to [35:20] of the 


4’18’ Sets the Low NCB Memory Base register to [35:20] of the 


4’19’ Sets the Low NCB Memory Limit register to [35:20] of the 


4’1A’ Sets the High NCB Memory Base register to [35:20] of the 


6–26 6878 7530–007

WIPS State 

Identifier 

High NCB Memory 

Limit 

Value 

Description 


4’1B’ Sets the High NCB Memory Limit register to [35:20] of the 


Byte Memory Base 4’1C’ Sets the Byte Memory Base register to [35:20] of the state 

value argument. 

Byte Memory Limit 4’1D’ Sets the Byte Memory Limit register to [35:20] of the state 

value argument. 

Libra 4000 System 

WIPS State 

Identifier 

Value Description 

Low Stack PL 3 Sets the performance level of low stack numbers as specified 

by the state value argument: 

[38:07] = Encoded timeout value for this performance level 

[31:08] = Stack number limit for this performance level 

[23:08] = Performance level 

[15:16] = 0 

Restricted I/O Support Operator 

BAFP (Libra 6xx and 7xx Systems) 

BAFP converts an IDD argument to an equivalent integer byte address that assumes Emode 

addressing. The integer mod 8 ranges from 0 to 5, where 0 refers to byte [47:8], 1 

refers to byte [39:8], and so forth, down to byte [7:8]. The integer mod 8 always equals 

zero when the argument is a word IDD. 

BAFP accepts a word (size < 2) or byte (size = 4) unpaged IDD. The IDD word index 

must be less than 2**16. BAFP returns an integer equal to 8 * + 8 

* + . 

 

Top-of-stack 

IndexedDD Integer 


 

6878 7530–007 6–27


Restricted Word Extension Operators 

Memory hardware on the CMP platform utilizes a 64-bit word. For ClearPath MCP 

processors, the TAG field has moved from [51:4] to [59:4]. Bits [55:4] are known as the 

word extension. Bits [63:4] and [51:4] are undefined. There is no change in the current 

hardware mechanism that supports bit addressing for bits [47:48]. 

Four pairs of operators are defined for accessing the word extension: 

• One pair to get or set the stack number in a normal SIRW/ENVW or HISW/TSCW 

• One pair to get or set the ASD reference in a touched descriptor or PCW/RCW 

• One pair to get or set the ASD reference in a pseudo SIRW/ENVW 

• One pair to get or set the word extension itself 

The GET operators accept a bit vector argument in TOS. The SET operators accept a bit 

vector argument in TOS2 and require an integer argument in TOS. 

GASF 

GASF returns a 27-bit integer consisting of TOS.extension in [26:4] and TOS.[19:23] in 

[22:23]. 

 

Top-of-stack 

any(bit vector) 27-bit integer 


 

SASF 

SASF inserts TOS.[26:4] in TOS2.extension and TOS.[22:23] in TOS2.[19:23]. 

 

 

Top-of-stack Integer 

 


 

any(bit vector) dest’ 

 

 

GASP 

GASP returns a 27-bit integer consisting of TOS.extension in [26:4] and TOS.[46:23] in 

[22:23]. 

 

Top-of-stack 



 

6–28 6878 7530–007

SASP 


SASP inserts TOS.[26:4] in TOS2.extension and TOS.[22:23] in TOS2.[46:23]. 

 

 


 


 


 

 

GSTN 

GSTN returns a 19-bit integer consisting of TOS.extension in [18:4] and TOS.[46:15] in 

[14:15]. 

 

Top-of-stack 



 

SSTN 

SSTN inserts TOS.[18:4] in TOS2.extension and TOS.[14:15] in TOS2.[46:15]. 

 

 


 


 


 

 

GEXT 

GEXT returns a 4-bit integer consisting of TOS.extension in [3:4]. 

 

Top-of-stack 



 

6878 7530–007 6–29


SEXT 

SEXT inserts TOS.[3:4] in TOS2.extension. 

 

 


 


 


 

 

6–30 6878 7530–007

Appendix A 

Alphabetical Operator Code List 

The following table lists all operators alphabetically by mnemonic. The operator 

mnemonic and name are followed by the hexadecimal encoding, operator type, and 

parameters, if any. For operators that are not valid on all ClearPath MCP systems, 

information concerning compatibility is provided. Operators that are restricted are also 

denoted as such. 

The operator type is indicated with the following notation: 

p primary operator 

v variant operator 

e edit mode operator (same encoding in table and single edit) 

se edit mode operator (single edit only) 

te edit mode operator (table edit only) 

Mnemonic Operator Name Hex 

Operator 

Type 

ADD Add 80 p 

AMAX Arithmetic maximum 958A v 

AMIN Arithmetic minimum 9588 v 

ASRT Assert 9580 v interrupt_ code:8 

AVER Aver 958F v 

BAFP Byte address from 

pointer 

BCD Binary convert to 

decimal 

BMS Bounded masked 

search for equal 

9577 v N:8 

95A9 v 

BRFL Branch false A0 p op_psi:3 

op_pwi:13 

BRST Bit reset 9E p Db:8 

BRTR Branch true A1 p op_psi:3 

op_pwi:13 

Code Stream 

Parameters Level/Feature 

v Restricted: Selected 

systems 

6878 7530–007 A–1



Operator 

Type 

BRUN Branch unconditional A2 p op_psi:3 

op_pwi:13 

BSET Bit set 96 p Db:8 

CBON Count binary ones 95BB v 

CEQD Compare characters 

equal delete 

CGED Compare characters 

greater or equal 

delete 

CGTD Compare characters 

greater delete 

F4 p 

F1 p 

F2 p 

CHEK Compute check-hash 95C8 v 

CHES Change emulation 

segment 

CHSN Change sign 8E p 

CLED Compare characters 

less or equal delete 

CLSD Compare characters 

less delete 

CNED Compare characters 

not equal delete 

Code Stream 


9595 v Restricted: Selected 

systems 

F3 p 

F0 p 

F5 p 

CPV Copy vector 95E0 v 

CPVA Copy vector absolute 95E2 v 

CPVD Copy vector double 95E4 v 

CPVN Copy vector negated 95E1 v 

CPVS Copy vector single 95E3 v 

CREL Character sequence 

relational 

CVS2 Convert sign 

magnitude to 2’s 

complement 

CV2S Convert 2’s 

complement to sign 

magnitude 

DBCD Dynamic binary 

convert to decimal 

DBFL Dynamic branch 

false 

95A8 v 

9554 v Level Epsilon 

9555 v Level Epsilon 

957F v 

A8 p 

DBRS Dynamic bit reset 9F p 

A–2 6878 7530–007


Operator 

Type 

DBST Dynamic bit set 97 p 

DBTR Dynamic branch true A9 p 

DBUN Dynamic branch 

unconditional 

DEXI Disable external 

interrupts 

DFTR Dynamic field 

transfer 

AA p 

9547 v 

99 p 

DINS Dynamic field insert 9D p 

DISO Dynamic field isolate 9B p 

DIVD Divide 83 p 

DLET Delete top of stack B5 p 

DOT Dot (inner) product-- 

single 

DOTX Dot (inner) product-- 

extended 

95C4 v 

95C5 v 

DRNT Dynamic range test 9583 v 

DUPL Duplicate top of 

stack 

EEXI Enable external 

interrupts 

B7 p 

9546 v 

ENDE End edit DE te 

ENDF End float D5 te MinusChar:8 

PlusChar:8 

ENTR Enter AB p 

EQUL Equal to 8C p 

EVAL Evaluate AC p 

EXCH Exchange top of 

stack 

B6 p 

EXIT Exit A3 p 

EXPU Execute single edit 

operator, single 

pointer update 

EXSD Execute single edit 

operator delete 

EXSU Execute single edit 

operator update 

DD p 

D2 p 

DA p 


Code Stream 


6878 7530–007 A–3



Operator 

Type 

Code Stream 


EXTB External branch 954C v Restricted: Selected 

systems 

FLTR Field transfer 98 p Db:8 Sb:8 Len:8 

FMN Find minimum 95CA v 

FMX Find maximum 95C9 v 

FMXA Find maximum 

absolute value 

95CB v 

GASF Get ASD field 9558 v Restricted: Epsilon 

GASP Get ASD pseudo 955A v Restricted: Epsilon 

GATH Gather 95C1 v 

GESZ Get element_size 95CF v 

GEXT Get extension 955E v Restricted: Epsilon 

GINX Get index 95CE v 

GLEN Get length 95CD v 

GREQ Greater than or equal 

to 

89 p 

GRTR Greater than 8A p 

GSTN Get stack number 955C v Restricted: Epsilon 

HALT Conditional 

processor halt 

ICLD Input convert leftsigned 

delete 

ICRD Input convert rightsigned 

delete 

ICUD Input convert 

unsigned delete 

95DF v Restricted 

9575 v 

9576 v 

A4 p 

ICVD Input convert delete CA p 

IDIV Integer divide 84 p 

IDLE Idle until interrupt 9544 v Restricted 

IMKS Insert mark stack CF p 

INDX Index A6 p 

INOP Insert overpunch D8 e 

INSC Insert conditional DD te Length:8 

ZeroChar:8 

NonZeroChar:8 

A–4 6878 7530–007


Operator 

Type 

INSG Insert display sign D9 e MinusChar:8 

PlusChar:8 

INSR Field Insert 9C p Db:8 Len:8 

INSU Insert unconditional DC se Char:8 

INSU Insert unconditional DC te Length:8 Char:8 


Code Stream 


IPST IP Status 9596 v Restricted: Selected 

systems 

ISOL Field isolate 9A p Sb:8 Len:8 

JOIN Join two operands 

into double 

9542 v 

LAND Logical AND 90 p 

LDNC Load no check 9594 v Restricted: Selected 

systems 

LDNO Load no check 

original 

LEQV Logical equivalence 93 p 

LESS Less than 88 p 

959B v Restricted: Selected 

systems 

LNMC Long name call 958C v lambda:4 delta:12 

LNOT Logical NOT 92 p 

LOAD Load BD p 

LODC Load character FD p 

LODT Load transparent BC p 

LODT Load transparent 95BC v 

LOG2 Leading one test 958B v 

LOR Logical OR 91 p 

LSEQ Less than or equal to 8B p 

LT8 Insert 8-bit literal B2 p constant:8 

LT16 Insert 16-bit literal B3 p constant:16 

LT48 Insert 48-bit literal BE p word-aligned 

constant:48 

LVLC Long value name call 958D v lambda:4 delta:12 

MCHR Move characters D7 se 

MCHR Move characters D7 te Length:8 

MFLT Move with float D1 se ZeroChar:8 

MinusChar:8 

PlusChar:8 

6878 7530–007 A–5



Operator 

Type 

MFLT Move with float D1 te Length:8 

ZeroChar:8 

MinusChar:8 

PlusChar:8 

MINS Move with insert D0 se ZeroChar:8 

MINS Move with insert D0 te Length:8 

ZeroChar:8 

MKSN Mark-stack bound to 

name-call 

DF p 

MKST Mark stack AE p 

MPCW Make PCW BF p word-aligned 

SkeletonPCW: 48 

MPWL Make PCW LL F6 p 

MPWP Make PCW LL+1 F7 p 

MULT Multiply 82 p 

MULX Extended multiply 8F p 

MVNU Move numeric 

unconditional 

MVNU Move numeric 

unconditional 

D6 se 

D6 te Length:8 

Code Stream 


MVST Move stack 95AF v Restricted 

NAMC Name call 40-7F p variable-fence 

address couple:14 

(two syllables 

total) 

NEQL Not equal to 8D p 

NMC0 Name call lambda 0 C4 p delta:16 




NOOP No operation FE p 

NOOP No operation 95FE v 

NORM Normalize 958E v 

NORX Disable reindex of 

reference 

NOWR Disable write via 

reference 

957C v 

957D v 

A–6 6878 7530–007


NTGD Integerize double 

precision rounded 

Operator 

Type 

9587 v 

NTGR Integerize rounded 87 p 

NTIA Integerize truncated 86 p 

NTTD Integerize double 

precision truncated 

9586 v 

NVLD Invalid operator FF p 

NVLD Invalid operator 95FF v 

NXLN Index and load name A5 p 

NXLV Index and load value AD p 

OCRX Occurs index 9585 v 

ONE Insert literal one B1 p 

OVRD Overwrite delete BA p 

OVRN Overwrite non-delete BB p 


Code Stream 


PAUS Pause until interrupt 9584 v Restricted 

PKLD Pack left-signed 

delete 

PKRD Pack right-signed 

delete 

PKUD Pack unsigned 

delete 

POLY Polynomial 

recurrence 

PUSH Push working stack 

onto activation 

record 

RASD Read ASD-table 

word 

RCMT Read and clear 

machine time of day 

clock 

9573 v 

9574 v 

9572 v 

95C7 v 

B4 p 

RDIV Remainder divide 85 p 

RDLK Read and lock 95BA v 

RDMT Read machine time 

of day clock 

REMW Read external 

memory word 

RETN Return A7 p 

95B1 v Restricted 

956B v Restricted: Selected 

systems 

956A v Restricted: Selected 

systems 


systems 

6878 7530–007 A–7



REXI Return/exit from 

interrupt 

Operator 

Type 

Code Stream 


95F7 v Restricted 

RIPS Read IP state 9598 v Restricted: Selected 

systems 

RIRR Read interrupt 

request register 


systems 

RMTR Read micro timer 9568 v Restricted: Selected 

systems 

ROFF Read and reset 

overflow flip-flop 

RPRR Read processor 

register 

D7 p 


RREG Read APIC register 9561 v Restricted: Selected 

systems 

RSDN Rotate stack down 95B7 v 

RSNR Read SNR 9581 v 

RSQR Real square root 9550 v 

RSTF Reset float flip-flop D4 e 

RSUP Rotate stack up 95B6 v 

RTAG Read tag 95B5 v 

RTFF Read true-false flipflop 

DE p 

RTN2 Return two items 95AE v 

RTOD Read real time of day 

clock 

95A7 v 

RUNI Indicate running 9541 v Restricted 

SAME Logical equality 94 p 

SASF Set ASD field 9559 v Restricted: Epsilon 

SASP Set ASD pseudo 955B v Restricted: Epsilon 

SCAT Scatter 95C0 v 

SCMP String compare 95AA v 

SCPY String copy 95AB v 

SCRD SLC read 9592 v Restricted: Selected 

systems 

SE4C Set element_size to 

hex characters 

95A0 v 

A–8 6878 7530–007


SE8C Set element_size to 

EBCDIC characters 

SEDW Set element_size to 

double words 

SEQ Sequential 

recurrence 

SEQD Scan while equal 

delete 

SEQU Scan while equal 

update 

SESW Set element_size to 

single words 

Operator 

Type 

95A1 v 

95A3 v 

95C6 v 

95F4 v 

95FC v 

95A2 v 


Code Stream 


SEXT Set extension 955F v Restricted: Epsilon 

SFDC Skip forward 

destination 

characters 

SFDC Skip forward 

destination 

characters 

SFSC Skip forward source 

characters 

SFSC Skip forward source 

characters 

SGED Scan while greater or 

equal delete 

SGEU Scan while greater or 

equal update 

SGTD Scan while greater 

delete 

SGTU Scan while greater 

update 

DA se 

DA te Length:8 

D2 se 


95F1 v 

95F9 v 

95F2 v 

95FA v 

SINT Set interval timer 9545 v Restricted 

SISO String isolate D5 p 

SLED Scan while less or 

equal delete 

SLEU Scan while less or 

equal update 

SLSD Scan while less 

delete 

95F3 v 

95FB v 

95F0 v 

6878 7530–007 A–9



SLSU Scan while less 

update 

SNED Scan while not equal 

delete 

SNEU Scan while not equal 

update 

SNGL Set to single 

precision rounded 

SNGT Set to single 

precision truncated 

SPLT Split operand into 

two singles 

SPRR Set processor 

register 

SRCH Masked search for 

equal 

SRDC Skip reverse 

destination 

characters 

SRDC Skip reverse 

destination 

characters 

SRSC Skip reverse source 

characters 

SRSC Skip reverse source 

characters 

Operator 

Type 

95F8 v 

95F5 v 

95FD v 

CD p 

CC p 

9543 v 

Code Stream 



95BE v 

DB se 

DB te Length:8 

D3 se 


SSTN Set stack number 955D v Restricted: Epsilon 

STAG Set tag 95B4 v 

STCD Store character 

delete 

STCN Store character 

nondelete 

F8 p 

F9 p 

STFF Stuff AF p 

STOD Store delete B8 p 

STON Store nondelete B9 p 

STOP Unconditional 

processor halt 

95BF v 

SUBT Subtract 81 p 

A–10 6878 7530–007


SUM Summation over 

vector 

SUMA Summation over 

vector, absolute 

SUMW Summation over 

vector, word 

SWFD Scan while false 

delete 

SWFU Scan while false 

update 

SWTD Scan while true 

delete 

SWTU Scan while true 

update 

SXSN Set external sign flipflop 

TEED Table enter edit 

delete 

TEEU Table enter edit 

update 

TEQD Transfer while equal 

delete 

TEQU Transfer while equal 

update 

TGED Transfer while 


delete 

TGEU Transfer while 


update 

TGTD Transfer while 

greater delete 

TGTU Transfer while 

greater update 

TLED Transfer while less 

or equal delete 

TLEU Transfer while less 

or equal update 

TLSD Transfer while less 

delete 

Operator 

Type 

95C2 v 

95C3 v 

95CC v 

95D4 v 

95DC v 

95D5 v 

95DD v 

D6 p 

D0 p 

D8 p 

E4 p 

EC p 

E1 p 

E9 p 

E2 p 

EA p 

E3 p 

EB p 

E0 p 


Code Stream 


6878 7530–007 A–11



TLSU Transfer while less 

update 

TNED Transfer while not 

equal delete 

TNEU Transfer while not 

equal update 

Operator 

Type 

E8 p 

E5 p 

ED p 

TRNS Translate 95D7 v 

TUND Transfer characters 

unconditional delete 

TUNU Transfer characters 

unconditional update 

TWFD Transfer while false 

delete 

TWFU Transfer while false 

update 

TWOD Transfer words 

overwrite delete 

TWSD Transfer words 

delete 

TWSU Transfer words 

update 

TWTD Transfer while true 

delete 

TWTU Transfer while true 

update 

UPLD Unpack left-signed 

delete 

UPLU Unpack left-signed 

update 

UPRD Unpack right-signed 

delete 

UPRU Unpack right-signed 

update 

UPUD Unpack unsigned 

delete 

UPUU Unpack unsigned 

update 

USND Unpack signed 

delete 

E6 p 

EE p 

95D2 v 

95DA v 

Code Stream 


D4 p Restricted 

D3 p 

DB p 

95D3 v 

95DB v 

9570 v 

9578 v 

9571 v 

9579 v 

95D1 v 

95D9 v 

95D0 v 

A–12 6878 7530–007


USNU Unpack signed 

update 

Operator 

Type 

95D8 v 

VALC Value call 00-3F p variable-fence 

address couple:14 

(two syllables 

total) 

VARI Introduce variant 

operator 

95 p 

VLC0 Value call lambda 0 C0 p delta: 16 




VMV Vector minus vector 95E6 v 

VMVN Vector minus vector 

negated 

VOV Vector over (divided 

by) vector 

95E7 v 

95E9 v 

VPS Vector plus scalar 95EB v 

VPV Vector plus vector 95E5 v 

VPVS Vector plus vector 

times scalar 

VSPV Vector times scalar 

plus vector 

95ED v 

95EE v 

VTS Vector times scalar 95EC v 

VTV Vector times vector 95E8 v 

VUV Vector under (divided 

into) vector 

WASD Write ASD-table 

word 

WATI Read machine 

identification 

WEMW Write external 

memory word 

95EA v 


Code Stream 



95A4 v Restricted 


systems 

WHOI Read proc_id 954E v Restricted 

WIPS Write IP State 9599 v Restricted: Selected 

systems 

WMTR Write Micro Timer 9569 v Restricted: Selected 

systems 

6878 7530–007 A–13



Operator 

Type 

Code Stream 


WREG Write APIC register 9562 v Restricted: Selected 

systems 

WTOD Write real time of 

day clock 

XTND Set to double 

precision 

9549 v Restricted 

CE p 

ZERO Insert literal zero B0 p 

ZIC Zero Interrupt_Count 9540 v Restricted 

A–14 6878 7530–007

Appendix B 

Boolean Accumulator X-Ref 

The operators that interact with the four Boolean Accumulators are listed with the type 

of interaction. 

TFFF (true/false flip-flop) 

left in undefined state by: 

TUND/TUNU, SCPY, CREL, SCMP, PKUD, ICUD, ICLD, ICRD, ICVD; 

defined value for required subsequent RTFF, but left in undefined state 

by: 

CGTD, CGED, CEQD, CNED, CLED, CLSD 

SGTD, SGED, SEQD, SNED, SLED, SLSD 

set by: 

character relational operators (except for scan delete): 

SGTU, SGEU, SEQU, SNEU, SLEU, SLSU, 

TGTD/TGTU, TGED/TGEU, TEQD/TEQU, TNED/TNEU, 

TLED/TLEU, TLSD/TLSU 

character set membership operators: 

SWTD/SWTU, SWFD/SWFU, TWTD/TWTU, TWFD/TWFU 

pack operators (except PKUD): 

PKLD, PKRD 

read by: 

RTFF 

6878 7530–007 B–1


OFFF (overflow flip-flop) 

conditionally set to 1 (true) by: 

BCD/DBCD 

read and reset to 0 (false) by: 

ROFF 

EXTF (external sign flip-flop) 

left in undefined state by: 

PKUD, ICUD, ICLD, ICRD, ICVD 

set by: 

BCD/DBCD, SXSN, PKLD, PKRD 

read by: 

unpack signed operators: 

UPLD/UPLU, UPRD/UPRU, USND/USNU 

edit sign operators: 

INOP, INSG, MFLT, ENDF 

FLTF (float flip-flop) 

reset to 0 (false) by: 

TEED/TEEU, EXSD/EXSU in initial mode and by RSTF 

read and conditionally set to 1 (true) by: 

MINS, MFLT 

read and reset to 0 (false) by: 

ENDF 

read by: 

INSC 

B–2 6878 7530–007

TFFF, OFFF, and EXTF 

FLTF 

saved in the stack frame linkage by: 

enter operations 

restored from that linkage by: 

exit operations 

preserved as restart information at service interrupts from: 

edit operators 

restored by: 

enter-edit operators in restart mode 


6878 7530–007 B–3


B–4 6878 7530–007

Appendix C 

Operator Encoding 

The processor has three modes of interpretation of a one-syllable operator code. 

• Primary mode is the default interpretation of one-syllable operating code. 

• Variant mode is enabled by interpretation of the primary mode operator encoding 

VARI (hex 95). VARI causes the processor to interpret the next syllable as a variant 

mode operator. Following execution of this operator, the processor reverts to 

primary mode. For convenience, variant operator encodings are written hex 95xx, 

where xx is the one-syllable variant operator code. 

• Edit mode is enabled by interpretation of the primary mode operators TEED, TEEU, 

EXSD, EXSU, and EXPU (hex D0, D8, D2, DA, and DD, respectively). TEED and TEEU 

cause the processor to interpret the syllables in an external table as edit mode 

operators, each of which is followed by associated parameters. The processor 

returns to primary mode following interpretation of ENDE (hex DE) operator in the 

table. EXSD, EXSU, and EXPU cause the processor to interpret the next syllable as 

an edit mode operator followed by associated parameters. Following execution of 

the edit mode operator, the processor returns to primary mode interpretation. 

The following charts show for each interpretation mode the operator associated with 

each syllable encoding. Unflagged mnemonics are unrestricted; flag characters denote 

obsolete or restricted operators: 

– obsolete 

+ partially restricted 

# restricted 

6878 7530–007 C–1


Primary Mode Operators 

0 1 2 3 4 5 6 7 

 

 

8 ADD SUBT MULT DIVD IDIV RDIV NTIA NTGR 

 

 

 

9 LAND LOR LNOT LEQV SAME VARI BSET DBST 

 

 

 

A BRFL BRTR BRUN EXIT ICUD NXLN INDX RETN 

 

 

 

B ZERO ONE LT8 LT16 PUSH DLET EXCH DUPL 

 

 

 

C VLCO VLC1 VLC2 VLC3 NMCO NMC1 NMC2 NMC3 

 

 

 

D TEED EXSD TWSD #TWOD SISO SXSN ROFF 

 

 

 

E TLSD TGED TGTD TLED TEQD TNED TUND 

 

 

 

F -CLSD -CGED -CGTD -CLED -CEQD -CNED MPWL MPWP 

 

 

C–2 6878 7530–007

Primary encodings are 00-3F are VALC; primary encodings 40-7F are NAMC. 

8 9 A B C D E F 

 

 

LESS GREQ GRTR LSEQ EQUL NEQL CHSN MULX 8 

 

 

 

-FLTR DFTR ISOL DISO INSR DINS BRST DBRS 9 

 

 

 

DBFL DBTR DBUN ENTR EVAL NXLV MKST STFF A 

 

 

 

STOD STON +OVRD +OVRN +LODT LOAD LT48 MPCW B 

 

 

 

ICVD SNGT SNGL XTND IMKS C 

 

 

 

TEEU EXSU TWSU EXPU RTFF -MKSN D 

 

 

 

TLSU TGEU TGTU TLEU TEQU TNEU TUNU E 

 

 

 

STCD STCN LODC NOOP NVLD F 

 

 


6878 7530–007 C–3


Variant Mode Operators 

0 1 2 3 4 5 6 7 

 

 

3 

 

 

 

4 #ZIC #RUNI JOIN SPLT #IDLE #SINT +EEXI +DEXI 

 

 

 

5 RSQR CVS2 CV2S 

 

 

 

6 #RIRR #RREG #WREG #REMW #WEMW 

 

 

 

7 UPLD UPRD PKUD PKLD PKRD ICLD ICRD BCD 

 

 

 

8 ASRT RSNR DRNT #PAUS -OCRX NTTD NTGD 

 

 

 

9 #SCRD #LDNC #CHES #IPST 

 

 

 

A SE4C SE8C SESW SEDW #WATI RTOD 

 

 

 

B #RASD #WASD +STAG RTAG RSUP RSDN 

 

 

 

C SCAT GATH SUM SUMA DOT DOTX SEQ POLY 

 

 

 

D -USND UPUD TWFD TWTD SWFD SWTD TRNS 

 

 

 

E CPV CPVN CPVA CPVS CPVD VPV VMV VMVN 

 

 

 

F SLSD SGED SGTD SLED SEQD SNED #REXI 

 

 

C–4 6878 7530–007

Variant encodings 00-2F are undefined. 

8 9 A B C D E F 

 

 

3 

 

 

 

#WTOD #EXTB #WHOI 4 

 

 

 

#GASF #SASF #GASP #SASP #GSTN #SSTN #GEXT #SEXT 5 

 

 

 

#RMTR #WMTR #RDMT #RCMT 6 

 

 

 

UPLU UPRU NORX NOWR DBCD 7 

 

 

 

AMIN AMAX LOG2 LNMC LVLC NORM AVER 8 

 

 

 

#RIPS #WIPS #LDNO #BAFP 9 

 

 

 

CREL BMS SCMP SCPY RTN2 #MVST A 

 

 

 

+RPRR #SPRR #RDLK CBON +LODT SRCH #STOP B 

 

 

 

CHEK FMX FMN FMXA SUMW GLEN GINX GESZ C 

 

 

 

-USNU UPUU TWFU TWTU SWFU SWTU #HALT D 

 

 

 

VTV VOV VUV VPS VTS VPVS VSPV E 

 

 

 

SLSU SGEU SGTU SLEU SEQU SNEU NOOP NVLD F 

 

 


6878 7530–007 C–5


Edit Mode Operators 

All edit operator encodings except D0--DF are undefined. 

0 1 2 3 4 5 6 7 

 

 

D MINS MFLT SFSC SRSC RSTF ENDF MVNU MCHR 

 

 

8 9 A B C D E F 

 

 

INOP INSG SFDC SRDC INSU INSC ENDE #HALT D 

 

 

C–6 6878 7530–007

Appendix D 

Data Type Formats 

Throughout this appendix, the first and second boxes represent the extension and tag, 

respectively. 

Single Precision, numericinterpretation 

 

 

0 

 

 

 

0 ms e 

 

x mantissa 

 

0 es p 

 

 

 

0 

 

 

tag 0 



exponent [44: 6] The power of eight to which the mantissa is scaled 

mantissa [38:39] The magnitude of the number before scaling 

6878 7530–007 D–1


Single Precision, ICW (Index Control Word) interpretation 

 

 

0 

 

 

 

0 

 

ICW_width ICW_limit ICW_offset 

 

0 

 

 

 

0 

 

 

tag 0 

ICW_width [47:16] The number of units in an element in the sequence 

ICW_limit [31:16] The number of elements in the sequence 

ICW_offset [15:16] The offset from the base of the record to the start of the 

sequence 

D–2 6878 7530–007

Double Precision, numeric interpretation 


 

 

0 

 

 

 

0 ms e 

1st 

x mantissa 

word 

1 es p 

 

 

 

0 

 

 

 

 

0 

 

 

 

0 

hi_ 

2nd mantissa 

exp 

word 1 

 

 

 

0 

 

 

1st word: 

tag 2 



exponent [44: 6] The low order 6 bits of the exponent 

mantissa [38:39] The integral portion of the mantissa 

2nd word: 

hi_order_exp [47: 9] The high order 9 bits of the exponent 

mantissa [38:39] The fractional portion of the mantissa 

6878 7530–007 D–3


Single or Double Precision, Boolean interpretation 

 

 

0 

 

 

 

0 

 

 

 

x 

 

 

 

0 b 

 

 

tag (0: single precision, 

2: double precision (2nd word ignored)) 

[0:1] Boolean value (0=false, 1=true) 

Actual Segment Descriptor, First Word (ASD1 

 

 

1 hlt 

 

 

 

0 ns 

 

address 

 

0 pp pIO 

 

 

 

0 0 

 

 

D–4 6878 7530–007

tag 8 


segment_type [47: 2] Segment’s memory type (see “Platform Memory”) 

present_to_proc [45: 1] Segment-is-present indicator for non-I/O access 


[44: 1] Reserved for co-existence 

hlt [43: 1] Enables switch-dependent halt when executing code 

from this segment 

not_stack [42: 1] Stack indicator (0=stack, 1=not stack) 

present_for_IO [41: 1] Segment-is-present indicator for use as an I/O buffer 


[40:1] Must be zero 

address [35:36] If present_to_proc and present_for_IO are both zero, the 

address field is interpreted by software; otherwise, it 

contains the base address of the actual segment 

Actual Segment Descriptor, Second Word (ASD2) 

 

 

1 n 

 

s y 

 

0 o b 

 

f b deficit AS_length 

 

0 t l 

 

e 

 

0 s 

 

 

tag 8 

[47: 8] Reserved for software use 

nybbles [39: 4] 4-bit frames in addition to net words 

deficit [36:16] Words less than AS_length-derived length 

AS_length [19:20] Actual-segment length in words 

6878 7530–007 D–5


Untouched CSD (Code Segment Descriptor) 

 

 

0 0 

 

 

 

0 0 

 

interpreted by software 

 

1 

 

 

 

1 

 

 

Touched CSD 

tag 3 

[47: 2] Binary 00 

[45:46] Interpreted by software 

 

 

1 1 

 

ASD 

 

1 ref 

 

ASD ASD_ref hi 

 

ref 0 lo 

 

ext 

 

0 c 

 

 

ASD_ref ext [ext] ASD_number ms 4 bits 

tag C 


[0 by convention] 

read_only [43: 1] Read-only bit (1=read-only) 



D–6 6878 7530–007

Untouched DD 


 

 

0 0 

 

 

 

1 0 

 

interpreted by software 

 

0 

 

 

 

1 

 

 

tag 5 

[47: 2] Binary 00 

[45:46] Interpreted by software 

Unindexed (Original or Copy) DD 

 

 

1 ro 

 

ASD 

 

1 ref s 

 

ASD i ASD_ref hi 

 

ref pg lo z 

 

ext e 

 

0 c 

 

 

6878 7530–007 D–7



tag (C=unpaged, E=paged) 


read_only [43: 1] Read-only bit (0=read/write, 1=read only) 

element_size [42: 3] The type of array element (0=single precision, 

1=double precision, 2=hex, 4=EBCDIC; 3,5,6,7 are 

invalid) 



IndexedWordDD (Indexed Word Data Descriptor) 

 

 

1 ro 

 

ASD 

 

1 ref 0 

 

ASD index ASD_ref hi 

 

ref pg lo 0 

 

ext 

 

1 rx d 

 

 


tag (D: unpaged, F: paged) 

reindex [44: 1] Controls indexing, Data Array, and set-element_size operators 

(0=disabled, 1=enabled) 


element_size [42: 3] The type of array element (0=single precision; 1=double 

precision). (2,4 denote IndexedCharDD; 3,5,6,7, are invalid) 

index [39:20] The word index from the base of the array to the referenced 

item 


D–8 6878 7530–007

IndexedCharDD (Indexed Character Data Descriptor) 


 

 

1 ro 

 

ASD 

c 

1 ref s 

h 

ASD i word_index ASD_ref hi 

a 

ref pg lo z 

r 

ext e 

 

1 rx 

 

 


tag (D: unpaged, F: paged) 

reindex [44: 1] Controls indexing, Data Array, and set-element_size 

operators (0=disabled, 1=enabled) 


element_size [42: 3] The type of array element (2=hex, 4=EBCDIC). (0,1 

denote IndexedWordDD; 3, 5, 6, 7 are invalid) 

char_index [39: 4] The index within the word of the referenced character 

word_index [35:16] The index from the base of the array to the word 

containing the referenced character 


6878 7530–007 D–9


Environment Link 

 

 

psl 

 

stack_num & stack_disp 

 

or 

 

seg_num & seg_disp 

num 

 

ext 

(see SIRW & ENVW) 

 

 

 

 

Normal Environment Link 

num ext [ext] stack_num ms 4 bits 

pseudolink [47:1] 0: denotes normal env_link 

stack_num [46:15] The stack_number identifying the stack containing the 

referenced location (ls 15 bits) 

stack_disp [31:16] The displacement from the base of the stack to the 

MSCW of the normal activation record 

Pseudo Environment Link 

num ext [ext] seg_num ms 4 bits 

pseudolink [47:1] 1: denotes pseudo env_link 

seg_num [46:23] The ASD_number identifying the segment containing the 

referenced location (ls 23 bits) 

[23:2] reserved 

seg_disp [21:6] The displacement from the base of the segment to the 

MSCW of the pseudo activation record 

D–10 6878 7530–007

Stuffed Indirect Reference Word (SIRW) 


 

 

0 

 

 

 

env 0 

 

link env_link offset 

 

ext 0 

 

 

 

1 

 

 

env_link ext [ext] Env_link ms 4 bits 

tag 1 

env_link [47:32] Designates activation record in which reference occurs (ls 

32 bits) 

offset [15:16] The offset from the base of the activation record to the 

referenced location 

SIRW with normal env_link 

 

 

0 0 

 

 

 

stk 0 

 

num stack_num stack_disp offset 

 

ext 0 

 

 

 

1 

 

 

6878 7530–007 D–11


SIRW with pseudo env_link 

 

 

0 1 

 

 

 

0 

seg 

seg_num offset 

num 

0 

ext seg_ 

disp 

 

1 

 

 

HISW (History Word) 

 

his 

0 0 opt dx ex 

 

 

 

stk 0 pop-opt of 

 

num stack_num history_disp or fl 

 

ext 0 action tf 

 

status 

 

1 _ rs b_e 

 

 

stk_num ext [ext] stack_num ms 4 bits 

tag 1 

[47: 1] must be zero 

stack_num [46:15] number of stack containing the HISW (ls 15 bits) 

history_disp [31:16] displacement of prior HISW in stack 

history_opt [15: 1] 0: no optimization; 1: new D[LL] = new F+1 

[14: 1] 0: no pop optimization; 1: top n memory stack items’ dp 

status in HISW; 

[13:6] n = 5 - # consecutive 0’s below bit 14; vector of dp bits 

follows 1 st 

1 below bit 14 

Action interpretation of 12:5 vald if no pop optimization: 

D–12 6878 7530–007

action_valid [12: 1] Action_status validity 

action_status [11: 4] Special actions taken by exit 

disable_ext [ 7: 1] Disable maskable externals when exit 

float_status [ 6: 2] Variant rs resumption status 

rs [ 4: 1] restart indicator (0=initial, 1=restart mode) 

extf [ 3: 1] EXTF (external sign flip-flop) 

offf [ 2: 1] OFFF (overflow flip-flop) 

tfff [ 1: 1] TFFF (true false flip-flop) 

block_exit [ 0: 1] (0=disarmed, 1=armed) 

ENVW (Environment Word) 


 

 

0 

 

 

 

0 

env 

env_link 

link 

1 

ext 

 

 

1 

 

 

env_link ext [ext] Env_link ms 4 bits 

tag 3 

env_link [47:32] Identifies the immediate global activation record (if lex_level > 0) 

(ls 32 bits) 

[15:16] undefined 

6878 7530–007 D–13


ENVW with normal env_link 

 

 

0 0 

 

 

 

stk 0 

 

num stack_num stack_disp 

 

ext 1 

 

 

 

1 

 

 

ENVW with pseudo env_link 

 

 

0 1 

 

 

 

seg 0 

 

num seg_num 

 

ext 1 seg_disp 

 

 

 

1 

 

 

D–14 6878 7530–007

Tag-4 Word and Tag-6 Word 


 

 

0 

 

 

 

1 

 

(may be interpreted as a bit vector) 

 

x 

 

 

 

0 

 

 

Program Control Word (PCW) Skeleton 

 

 

cs 

 

 

 

psi 0 

 

0 pwi sdi 

 

sdl 

 

 

 

11 

 

 

[47:12] Zero 

skeleton_psi [35: 3] The PSI code stream pointer component 

skeleton_pwi [32:13] The PWI code stream pointer component 

skeleton_CS [19: 1] The initial value of the CS Boolean 

(0=normal state, 1=control state) 

[18: 1] Must be 0 in user programs 

skeleton_LL [17: 4] The lex level for the new activation record 

sdll [13: 1] The lambda component of an address couple designating 

the CSD 

sdi [12:13] The delta component of an address couple designating 

the CSD 

6878 7530–007 D–15


Program Control Word (PCW) 

 

 

0 0 

ASD p 

s 

ref i 

1 0 

ASD 

pwi 11 ASD_ref hi 

ref 

1 lo cs 

ext 

 

 

1 0 psi 0 

 

 


tag 7 

[44: 3] zero (for expansion: ASD_ref, pwi, or exit_opt) 


psi [28: 3] The PSI code stream pointer component 



lex_level [23: 4] The lex_level for the new activation record 


D–16 6878 7530–007

Return Control Word (RCW) 


 

 

0 0 

ASD p 

s 

ref i 

ASD 1 0 

 

ref pwi 11 ASD_ref hi 

 

ext 1 lo cs 

 

 

 

1 0 psi e_o 

 

 


Tag 7 

[44: 3] zero (expansion: ASD_ref, pwi, or exit-) 


psi [28:23] The PSI code stream pointer component 


exit_opt [24: 1] 0: no optimization information 

l: same global environment 

lex_level [23: 4] The lex_level at which the activation record runs 


6878 7530–007 D–17


Top of Stack Control Word (TSCW) 

 

 

0 0 

 

 

 

stk 0 

 

num stack_num history_disp offset 

 

ext 1 

 

 

 

1 

 

 

stk_num ext [ext] Stack_num ms 4 bits 

tag 3 


stack_num [46:15] The stack_number identifying the stack containing the 

TSCW 

history_disp [31:16] Displacement to the topmost HISW 

offset [15:16] Offset of top of stack from topmost HISW 

D–18 6878 7530–007

Absolute Store Reference Word (ASRW) 


 

 

1 

 

 

 

0 

 

address 

 

1 

 

 

 

1 

 

 

Tag B 


address [38:39] Address of memory item 

Soft POW 

 

 

1 

 

 

 

0 0 

 

reserved for software 

 

1 

 

 

 

0 

 

 

tag A 

[46: 1] 0: denotes software POW 


6878 7530–007 D–19


Hard POW 

 

 

1 1 

 

 

 

0 1 

 

reserved for system 

 

1 

 

 

 

0 

 

 

Restart POW 

tag A 

[47: 2] Binary 11: denotes hardware POW 

[45: 46] Reserved for system 

 

 

1 0 

 

 

 

0 1 

 

reserved for hardware 

 

1 0 

 

 

 

0 1 

 

 

tag A 

[47: 4] Binary 0101: denotes restart POW 

[43:44] Reserved for hardware 

D–20 6878 7530–007

Appendix E 

Processor Features Operators 

The very restricted operators in this group are not used by user programs nor by most of 

the released software. They fall into two types: 

• Those that bring data into caches to accomplish a hardware design-specific purpose 

• Those that access the processor state used for performance measurement 

LDNC 

The restricted operator LDNC performs a single evaluation of an IDD, ASRW, or integer 

reference in TOS, but the target is not left on top of the stack. It provides the ability to 

change cache contents without detecting target memory errors. Data addressed by 

LDNC, that is not initially local in the first-level cache, is placed in the second-level cache 

as a copy unless it is already there as an original. If there is a structural problem with a 

correctly typed reference (for example, absent segment or bounds violation), no interrupt 

is generated. 

 

Top-of-stack 

ref: IDD, ASRW, integer Null 


 

LDNO 

The restricted operator LDNO is identical to LDNC, except that it places data in the 

second-level cache as an original rather than a copy. 

 

Top-of-stack 

ref: IDD, ASRW, integer Null 


 

6878 7530–007 E–1

Processor Features Operators 

RMTR 

The restricted operator RMTR leaves on top of the stack a 48-bit vector which is the 

integer value of the executing processor’s Micro Timer, which counts at the processor 

clock rate. 

 

Top-of-stack 

Null sp 


 

SCRD 

The restricted operator SCRD requires one 7-bit integer argument, which is interpreted 

as an SLC register identification. The result left on top of the stack is the value of the 

specified register. 

 

Top-of-stack 

reg-id: sp(integer) sp(integer) 


 

SCRD is intended for use only in temporary system evaluation procedures using 

algorithms provided by hardware designers. 

WMTR 

The restricted operator WMTR requires a 48-bit vector on top of the stack. WMTR sets 

the executing processor’s Micro Timer to the value of the argument, treating it as a 48bit 

integer. The Micro Timer counts at the processor clock rate. 

 

Top-of-stack 

timer-value: sp Null 

tranformation: 

 

E–2 6878 7530–007

Appendix F 

Operator and Common Action 

Reference 

This appendix lists each operator and common action, in alphabetical order by 

mnemonic. (Common actions have mnemonics beginning with lowercase "a.") Several 

common actions are defined here for the purpose of consolidating the interrupt 

information for similar operations. Refer to "Common Actions" in Section 5 for more 

information. 

If the operator is fully restricted, that fact is indicated after the operator name. The 

following information follows the name line: 

p primary operator 

v variant operator 

e edit mode operator (same encoding in table and single edit) 

se edit mode operator (single edit only) 

te edit mode operator (table edit only) 

• The opcode is presented in hexadecimal notation, except for NAMC and VALC, 

which are in binary. 

• Any code-stream parameters are defined following the opcode, separated by 

ampersands. 

• If there are no ODI interrupts listed for this operator, a reference to another operator, 

or some other indication, appears at the right. 

• Similar operators that generate the same interrupts are treated as a group, with one 

operator representing the rest of the group. Each represented operator refers to the 

representative, under which all the members of the group are named. Citations of 

the group take the form "DBUN etc." or "DBFL & DBTR" when there are only two in 

the group. An operator (like DBUN) "partly" represents others (like DBFL and DBTR) 

that can generate all the same interrupts plus more. 

An instance of an operator-dependent interrupt is defined as a triple: an operator 

generates an interrupt for a reason. The interrupts and reasons are listed in this 

appendix under each operator and common action. All interrupts are summarized in 

Appendix G; the same instance triples are shown there by listing the operators/actions 

and reasons under each ODI. 

6878 7530–007 F–1

Operator and Common Action Reference 

A similar triple defines the relationship of a common action to its client operators: a client 

invokes a common action for a reason. The same triples are shown twice in this 

appendix: the clients and reasons are listed under each common action; the actions and 

reasons are listed under each operator. 

For both interrupt instances and common action relationships, the form and content of 

the "reason" varies with the context. A typical interrupt entry shows the infraction and/or 

the data structure involved. A typical common action entry shows the purpose of the 

invocation and/or the "actual parameters": a common action is conceptually a "procedure" 

and most operate on "formal parameters." 

The following notation is used in this appendix and Appendix G. 

> = designates directly (via an ASD_number) 

>> = designates indirectly (through an ASD or a display register) 

[...] = indexed by ... (said of descriptors and the ASD table) 

< > = not equal 

... = absolute value 

’ marks the update source/dest/edtab argument (internal or 

stack result) 

ActSegLen(x): actual segment length: 

ASD2.AS_length from ASD designated by x 

(default x is the object under discussion) 

anticipation: action performed before need 

exhausted: pointer designates last+1 element of virtual segment 

Mem[x]: the contents of the memory location at absolute address x 

PageTable = unpaged unindexed SingleDD defining a page table: 

created from paged unindexed DD 

or from ASD3 referenced by paged indexed DD 

by effectively resetting tag and element_size 

Stk[x] = Mem[ASD1[SNR].address+x] 

Unless restart mode is specified explicitly, the interrupt descriptions that follow apply to 

the operator in initial mode. 

This appendix and Appendix G define ODIs; most of these cases for unrestricted 

operators are detected on all ClearPath MCP systems. 

F–2 6878 7530–007

aACCE 


This common action enters the procedure when a PCW is encountered in a reference 

chain. Refer to "Procedure Entry Operators" in Section 5 for more information on aACCE. 

Clients: 

EVAL 

STOD & STON: SIRW >> {PCW} 

VALC etc.: parameter or SIRW >> {PCW} 

Interrupts: 

See aEVCH: display update 

See aPRCW: distribute entry PCW code-stream pointer 

aAPIX 

This common action is a procedure with two formal parameters: a DD and an index value 

vI to be applied to the DD. The index value is a number of elements for the described 

array. Some clients pass I2DDs as I1DDs in order to reindex them in units of single 

words. Refer to "aAPIX " in Section 5 for more information. 

The actual parameters for each invocation are shown as "DD by vI". For Data Array 

operators with an effective length of zero, vI is changed to zero and no interrupts are 

generated. 

6878 7530–007 F–3


Clients: 

aCHAR: client ICDD (as I1DD) by +1 

aFOP, aSOP: client I2DD (as I1DD) by +1 (to access 2nd word) 

BMS: current domain by -1 

CHEK: current vector_A by stride_A 

CPV etc., CPVD, 

CPVS, DOT, DOTX: current vector_A by stride_A 

current vector_B by stride_B 

FMN, etc.: current vector_A by stride_A 

GATH: current vector_A by stride_A 

vector_B argument by referent(vector_I) 

current vector_I by +1 

INDX, NXLN, 

and NXLV: DD argument by RaI(index argument) 

POLY: current vector_A by stride_A 


REMW: source UDD by (source index)/2 

SCAT: vector_A argument by referent(vector_I) 



SEQ: current vector_A by stride_A 


SESW & SEDW 

SE8C & SE4C: argument pointer by 0 (after element_size change) 

SFDC: current dest ICDD by +max(length,0) 

SFSC: current source ICDD by +max(length,0) 

SNGT IDD argument by 0 

SRCH: current domain by -1 

SRDC: current dest ICDD by -max(length,0) 

SRSC: current source ICDD by -max(length,0) 

SUM, SUMA, SUMW: current vector_A by stride_A 

SWFD etc.: set by WordIndex(c) 

TRNS: trtab by WordIndex(c) 

TWFD etc.: set by WordIndex(c) 

TWOD: current source or dest pointer (as I1DD) by +1 

TWSD & TWSU: current source or dest pointer (as I1DD) by +1 

VMV, VMNV, VOV, 

VPS, VPV, VPVS, 

VSPV, VTS, VTV, 

VUV: current vector_A by stride_A 


WEMW: dest UDD by (dest index)/2 

XTND: IDD argument by 0 

Interrupts: 

Absent Data: client paged unindexed DD (page table) 

ASD3 for client paged indexed DD (page table) 

Bounds Error: The following conditions detected by aAPIX cause client to generate 

interrupt if resulting (unrepresentable) DD is used or returned: 

new virtual index < 0 

unpaged DD and new index >= 2**20 

unpaged CharDD and new word index >= 2**16 

new page index >= ActSegLen(PageTable) 

Structure Error: ASD3 for paged indexed DD is not unpaged indexed DD 

(not checked if page index already known) 

ASD3 > not ASD1/ASD2 (page table) 

paged unindexed DD > not ASD1/ASD2 (page table) 

PageTable[new page index] 

not {unpaged unindexed DD, untouched DD} 

Touch Reference: PageTable[new page index] is untouched DD 

F–4 6878 7530–007


For convenience, Bounds Error conditions arising from attempts to generate 

unrepresentable indexed DDs are shown under aAPIX. However, not every instance can 

occur for every client; some pass only IWDDs or ICDDs; some can only increase or only 

decrease the virtual index. Furthermore, errors cannot be reported unless the indexed 

DD is evaluated or returned, so the actual interrupt generation is the responsibility of the 

client. For example, non-edit array operators that index a pointer or vector in anticipation 

of another iteration cannot generate an interrupt unless the anticipated iteration (or 

pointer update) occurs. 

aCHAR 

This interrupt-consolidation common action accesses the designated word via an ICDD 

and advances the ICDD to designate the successor word. 

The clients are all the non-edit character operators and the edit operators that move data. 

Note that these operators all coerce IWDD pointers to ICDDs. If the effective length is 

zero, the aAPIX index is zero and no interrupts are generated. 

Clients: 

CEQD etc., 

CREL & SCMP: access word via source1 or source2 ICDD 

ICUD etc.: access word via source ICDD 

INSU etc.: access word via dest ICDD 

MCHR etc.: access word via source or dest ICDD 

PKUD etc.: access word via source ICDD 

SCPY: access word via source or dest ICDD 

SEQD etc., SISO, SWFD etc.: access word via source ICDD 

TEQD etc., TRNS, TUND & TUNU, 

TWFD etc.: access word via source or dest ICDD 

UPUD etc.: access word via dest ICDD 

Interrupts: 

See aAPIX: client ICDD (as I1DD) by +1 

See aEIXD: evaluate current client ICDD 

Inv Target: client dest ICDD >> not operand 

client source ICDD >> not operand 

6878 7530–007 F–5


aEIRW 

This common action performs basic evaluation of an SIRW. 

Clients: 

aFOP: evaluate client SIRW 

aINTE: evaluate SIRW at F+2 or successor SIRW 

aSOP: evaluate client SIRW 

DBUN etc.: evaluate SIRW 

ENTR: evaluate SIRW at F+2 or successor SIRW 

EXTB: evaluate D[0] address couple to MEI PCW 

EVAL, INDX, LODT, 

MPWL & MPWP, NXLN, 

NXLV, OVRD etc., STOD 

& STON: evaluate SIRW 

Interrupts: 

See aEVLK: SIRW environment_link evaluation 

Bounds Error: displacement+offset >= ActSegLen 

aEIXD 

This interrupt-consolidation common action performs basic evaluation of an indexed DD. 

Clients: 

aCHAR: evaluate current client ICDD 

aFOP & aSOP: evaluate client IDD 

BMS: evaluate current domain 

LODC, LODT, 

MPWL & MPWP: evaluate IDD 

INDX & NXLN: evaluate final indexed DD 

OVRD etc.: evaluate IDD 

REMW: evaluate final indexed source DD 

SRCH: evaluate current domain 

STCD & STCN: evaluate IDD 

SWFD etc.: evaluate set[WordIndex(c)] 

TRNS: evaluate trtab[WordIndex(c)] 

TWFD etc.: evaluate set[WordIndex(c)] 

TWOD: evaluate current source or dest pointer 

TWSD & TWSU: evaluate current source or dest pointer 

WEMW: evaluate final indexed dest DD 

Interrupts: 

Absent Data: client indexed DD 

ASD3 for client paged index DD (page table) 

Bounds Error: word index >= ActSegLen 

(except when ultimate client can generate 

Source or Destination Boundary interrupt) 

page index >= ActSegLen(PageTable) 

Structure Error: client indexed DD ---> not ASD1/ASD2 

ASD3 for paged indexed DD is not unpaged indexed DD 

(not checked if page index already known) 

ASD3 ---> not ASD1/ASD2 (page table) 

PageTable[page index] not {unpaged unindexed DD, 

untouched DD} 

Touch Reference: PageTable[page index] is untouched DD 

F–6 6878 7530–007

aEVCH 


This common action consolidates the interrupts generated in traversing the 

environmental chain. 

Clients: 

aACCE, aINTE, MVST 

ENTR, EXIT etc.: display update 

Interrupts: 

See aEVLK: ENVW environment-link evaluation 

Structure Error: for each AR traversed on environmental chain: 

ENVW.env_link or D register >> not entered ENVW 

aEVLK 

This common action affects the basic evaluation of an Environmental Link. 

Clients: 

aEIRW: SIRW environment-link evaluation 

aEVCH: ENVW environment-link evaluation 

Interrupts: 

Absent Data: if pseudolink = 0: 

ASD1[stack_num].present_to_proc = 0 

if pseudolink = 1: 

ASD1[seg_num].present_to_proc = 0 

Bounds Errors: displacement >= ActSegLen 

Structure Error: if pseudolink = 0: 

stack_num > not ASD1/ASD2 


seg_num > not ASD1/ASD2 

aFOP 

This common action fetches an operand value via an SIRW, address-couple parameter, 

IWDD, or ICDD. Refer to "Read Evaluation Operators" in Section 5 for more information 

on aFOP. Validity checking of the target is performed by aFOP except when a nonoperand 

value must be examined by the client as a possible reference or valid target; 

aFOP returns any non-operand argument to the client when fetching: 

• For VALC etc. via address-couple parameter or SIRW 

• For LOAD via SIRW or I1DD or ICDD 

For vector operators with a zero length, aFOP does nothing. 

6878 7530–007 F–7


Clients: 

CHEK: fetch via current vector_A 

CPV etc., 

CPVD, CPVS: fetch via current vector_B 

DOT, DOTX: fetch via current vector_A or vector_B 

FMN etc.: fetch via current vector_A 

GATH: fetch via current vector_B or vector_I 

LOAD: fetch via SIRW or IDD 

NXLV: fetch via final indexed DD 

POLY: fetch via current vector_A or vector_B 

SCAT: fetch via current vector_B or vector_I 

SEQ: fetch via current vector_B 

SUM, SUMA, SUMW: fetch via current vector_A 

VALC etc.: fetch via parameter or subsequent reference 

VMV, VMVN, VOV: fetch via current vector_A or vector_B 

VPS: fetch via current vector_B 

VPV, VPVS, VSPV: fetch via current vector_A or vector_B 

VTS: fetch via current vector_B 

VTV, VUV: fetch via current vector_A or vector_B 

Interrupts: 

See aAPIX: client I2DD (as I1DD) by +1 (to access 2nd word) 

See aEAC: evaluate parameter for client VALC etc. 

See aEIRW: evaluate client SIRW 

See aEIXD: evaluate client IDD 

Inv Target: 2nd word via SIRW or address couple not operand 

I1DD >> not operand (except for LOAD) 

I2DD >> not operand 

ICDD >> not operand (except for LOAD) 

2nd word via I2DD not operand 

aINTE 

This common action generates an interrupt, which is implemented as entry to an 

operating-system procedure designated by a processor-generated reference. 

Thereference is an SIRW whose env_link and offset fields are set according to the 

interrupt situation. 

The action can be defined as four steps: 

1. Invoke MKST 

2. Place the interrupt reference on the stack (at Mem[F+2]) 

3. Place any parameter words on the stack 

4. Invoke ENTR 

Clients (not listed): all operations that generate interrupts 

Interrupts: 

See aEIRW: evaluate SIRW at F+2 or successor SIRW 



Missing PCW: SIRW >> not {SIRW, PCW} 

F–8 6878 7530–007

aPOAV 


This common action consolidates the interrupts generated during the validation of the 

arguments to pointer operators. The action can be described as a procedure with two to 

four formal parameters, each of which names an argument to be validated. The 

arguments for each client operator are listed in order up the stack (TOS last). The valid 

type or set of types for each argument (except length) is appended to the name. For 

length, the upper limit is specified. 

The clients are all non-edit pointer operators and the enter-edit operators, which validate 

arguments for edit operators. The term "pointer" is interpreted only here to include 

unindexed copy DDs. 

6878 7530–007 F–9


Clients: 

CEQD etc., CREL & 

SCMP: validate source1:pointer, source2:{pointer,opnd}, 

length:MaxInx 

EXPU: validate dest:pointer, length:MaxInx 

EXSD & EXSU: validate dest:pointer, source:{pointer, opnd}, 

length:MaxInx 

ICUD etc.: validate source:{pointer, opnd}, length:23 

PKUD etc.: validate source:{pointer, opnd}, length:24 

SCPY: validate dest:pointer, source:{pointer, opnd}, 

length:MaxInx, delim:sp operand 

SEQD etc.: validate source:{pointer, opnd}, 


SISO: validate source:{pointer,opnd}, 

length:{if source is hex then 24 else 12) 

SWFD etc.: validate source:{pointer,opnd}, 

length:MaxInx, set:I1DD 

TEED & TEEU: validate dest:pointer, source:{pointer, opnd}, 

edtab: unpaged indexed DD 

TEQD etc.: validate dest:pointer, source:{pointer, opnd}, 


TRNS: validate dest:pointer, source:{pointer, opnd}, 

length:MaxInx, trtab:I1DD 

TUND & TUNU: validate dest:pointer, source:{pointer, opnd}, 

length:MaxInx 

TWFD etc.: validate dest:pointer, source:{pointer, opnd}, 


TWOD: validate dest:{pointer,ASRW}, 

source:{pointer,ASRW,opnd} 

length:MaxInx 

TWSD & TWSU: validate dest:pointer, source:{pointer, opnd}, 

length:MaxInx 

UPUD etc.: validate dest:pointer, source:operand, length:MaxInv 

(Note: other ClearPath MCP systems detect length >24) 

Interrupts: 

Bounds Error: for client source or destination pointer 

(blocked by zero-length operator that deletes 

its arguments) 

IWDD.index > ActSegLen 

ICDD.word_index > ActSegLen 

ICDD.word_index = ActSegLen and .char_index > 0 

IWDD.index >= 2**16 

and client is not Transfer Words 

Inv Arg/Par: client length not operand or RaI(length) > limit 

client argument not specified type 

reindex disabled in client indexed DD 

(source, dest, set, trtab, or edtab) 

Structure Error: ASD3 for client paged indexed DD is not unpaged 

indexed DD (not checked if page index known) 

Uninit Arg: client argument tag in {6, 4} 

F–10 6878 7530–007

aPRCW 


The common action aPRCW distributes a code stream pointer from a PCW or RCW, as 

follows: 

1. PSN is set from the ASD_ref field of the PCW or RCW. 

2. PWI and PSI are set from the pwi and psi fields, respectively. PWI must be in the 

range {0 to ASD2.AS_length-1} for the ASD referenced by the new PSN value; PSI 

must be in the range {0 to 5}. 

3. If ASD1.present_to_proc is not set in the ASD designated by the new PSN value, an 

Absent Code interrupt is generated. 

Clients: 

aACCE, aINTE: distribute entry PCW code-stream pointer 

DBUN etc.: distribute branch-dest PCW code-stream pointer 

ENTR: distribute entry PCW code-stream pointer 

EXIT etc.: distribute RCW code-stream pointer 

EXTB: distribute MEI PCW code-stream pointer 

Interrupts: 

Absent Code: PCW or RCW 

Bounds Error: (PCW or RCW).pwi >= ActSegLen (only detected if code reference fails) 

(PCW or RCW).psi > 5 

Structure Error: PCW or RCW > not ASD1/ASD2 

aSOP 

This common action stores an operand value for operators that perform store evaluation 

of references. Refer to "Normal Store Operators" in Section 5 for more information on 

aSOP. aSOP accepts two formal parameters: the value to be stored and the reference. 

When the reference is an SIRW, the client (normal store) operator verifies that the target 

is a Data Word. 

For vector operators with a zero length, aSOP does nothing. 

6878 7530–007 F–11


Clients: 

CPV etc., CPVD, CPVS, 

GATH, SCAT, SEQ: store via current vector_A 

STOD & STON: store via SIRW or IDD 

VMV, VMVN, VOV, VPS, 

VPV, VPVS, VSPV, 

VTS, VTV, VUV: store via current vector_A 

Interrupts: 

See aAPIX: client I2DD (as I1DD) by +1 (to access 2nd word) 

See aEIRW: evaluate client SIRW 

See aEIXD: evaluate client IDD 

Inv Access: read_only IDD 

Inv Arg/Par: object is sp and reference is I2DD 

object is sp and SIRW >> dp opnd 

object is dp and reference is I1DD or ICDD 

object is dp and SIRW >> {sp opnd, tag-6 word, 

tag-4 word} 

Inv Target: IDD >> not Data Word (STOD & STON do not check) 

2nd word not Data Word (STOD & STON do not check) 

aVOAV 

This common action consolidates the interrupts generated during the validation of the 

arguments to vector operators. The action can be described as a procedure with four to 

six formal parameters, each of which names an argument to be validated. The 

arguments for each client operator are listed in order up the stack (TOS last). The valid 

type or set of types is appended to each name, except for length and stride arguments, 

which have fixed type. 

Additional type checking is defined under several vector operators to enforce 

consistency of precision between arguments. Many of these checks are in anticipation 

of the type checking in aSOP. 

F–12 6878 7530–007

Clients: 

CHEK: validate vector_A:I1DD, length, stride_A, 

hash:sp operand 

CPV etc.: validate vector_A:IWDD, vector_B:{IWDD,opnd}, 

length, stride_A, stride_B 

CPVD: validate vector_A:I2DD, vector_B:IWDD, 


CPVS: validate vector_A:I1DD, vector_B:IWDD, 


DOT: validate vector_A:I1DD, vector_B:I1DD, length, 

stride_A, stride_B, sum:sp operand 

DOTX: validate vector_A:IWDD, vector_B:IWDD, length, 

stride_A, stride_B, sum:dp operand 

FMN etc.: validate vector_A:IWDD, length, stride_A, 

X:sp operand, V:operand 

GATH: validate vector_A:IWDD, vector_B:IWDD, 

length, stride_A, vector_I:I1DD 

POLY: validate vector_A:IWDD, vector_B:{IWDD, opnd}, 

length, stride_A, stride_B, Z:operand 

SCAT: validate vector_A:IWDD, vector_B:{IWDD, opnd}, 

length, vector_I:I1DD, stride_B 

SEQ: validate vector_A:IWDD, vector_B:{IWDD,opnd}, 


SUM & SUMA: validate vector_A:IWDD, length, stride_A, 

sum:operand 

SUMW: validate vector_A:I1DD, length, stride_A, 

sum:operand 

VMV, VMVN, VOV: validate vector_A:IWDD, vector_B:{IWDD,opnd}, 


VPS: validate vector_A:IWDD, vector_B:IWDD, 

length, stride_A, stride_B, S:operand 

VPV: validate vector_A:IWDD, vector_B:{IWDD,opnd}, 


VPVS: validate vector_A:IWDD, vector_B:IWDD, 


VSPV: validate vector_A:IWDD, vector_B:{IWDD,opnd}, 


VTS: validate vector_A:IWDD, vector_B:IWDD, 


VTV, VUV: validate vector_A:IWDD, vector_B:{IWDD,opnd}, 


Interrupts: 


Inv Arg/Par: client length not sp integer or length > MaxInx 

client stride not sp integer 

or stride > MaxInx 

(client stride)*(restart count) > MaxInx 

(restart mode) 


client vector IWDD reindex disabled 

Structure Error: ASD3 for client paged indexed DD is not unpaged 


Uninit Arg: client argument tag in {6, 4} 

6878 7530–007 F–13


ADD 

p 80 

Arith Overflow: R(x+y) = TooBig [Exponent Overflow] 

Inv Arg/Par: x (TOS2) not operand or y (TOS) not operand 

Uninit Arg: TOS or TOS2 tag in {6, 4} 

AMAX 

v 958A 

also represents AMIN 



AMIN 

v 9588 See AMAX 

ASRT 

v 9580 & interrupt_code:8 See AVER 

AVER 

v 958F 

also represents ASRT 

False Assertion: Boolean (TOS) is False 

BAFP (restricted) – (Libra 680 and 690 

Systems) 

v 959C 

Inv Arg/Par: TOS not IDD 

BCD 

v 9577 & N:8 

Int Overflow: RId(B) = TooBig 

Int Arg/Par: B (TOS) not operand 

Uninit Arg: TOS tag in {6, 4} 

BMS 

v 95A9 

See aAPIX: current domain by -1 

See aEIXD: evaluate current domain, if length > 0 

Inv Arg/Par: length (TOS) not operand or RaI(length) > MaxInx 

domain (TOS2) not I1DD 

domain reindex disabled 

Structure Error: ASD3 for paged indexed domain is not unpaged indexed 

DD (not checked if page index known) 

Uninit Arg: length or domain tag in {6, 4} 

F–14 6878 7530–007

BRFL 


p A0 & op_psi:3 & op_pwi:13 See BRUN 

BRST 

p 9E & Db:8 No interrupts 

BRTR 

p A1 & op_psi:3 & op_pwi:13 See BRUN 

BRUN 

p A2 & op_psi:3 & op_pwi:13 

also represents BRFL & BRTR 

Bounds Error: op_pwi >= ActSegLen(PSN) 

op_psi > 5 

BSET 

p 96 & Db:8 No interrupts 

CBON 

v 95BB 

Inv Arg/Par: TOS not operand 


CEQD 

p F4 

also represent CGED, CGTD, CLED, 

CLSD, CNED, CREL, SCMP 

See aCHAR: access word via source1 or source2 ICDD 

See aPOAV: validate source1:pointer, source2:{pointer, opnd}, 

length:MaxInx 

Inv Arg/Par: source1 is EBCDIC and source2 is hex or vice versa 

CGED 

p F1 See CEQD 

CGTD 

p F2 See CEQD 

CHEK 

v 95C8 

See aAPIX: current vector_A by stride_A 

See aFOP: fetch via current vector_A 

See aVOAV: validate vector_A:I1DD, length, stride_A, 

hash:sp operand 

6878 7530–007 F–15


CHES (restricted) – (Libra 680 and 690 

Systems) 

v 9595 

Absent Data: PCW 

Bounds Error: ASD2[PCW.ASD_ref].AS_length not ASD1/ASD2 

ASD1[PCW.ASD_ref].address mod 2**13 >0 

CHSN 

p 8E 



CLED 

p F3 See CEQD 

CLSD 

p F0 See CEQD 

CNED 

p F5 See CEQD 

CPV 

v 95E0 

also represents CPVA, CPVN 



See aFOP: fetch via current vector_B 

See aSOP: store via current vector_A 

See aVOAV: validate vector_A:IWDD, vector_B:{IWDD,opnd} 


Inv Arg/Par: vector_A is sp and vector_B is dp or vice versa 

CPVA 

v 95E2 See CPV 

CPVD 

v 95E4 





See aVOAV: validate vector_A:I2DD, vector_B:IWDD, 


F–16 6878 7530–007

CPVN 


v 95E1 See CPV 

CPVS 

v 95E3 




See aSOP: fetch via current vector_A 

See aVOAV: validate vector_A:I1DD, vector_B:IWDD, 


Vect Arith Exc: RS(ND(B(i))) = TooBig [Exponent Overflow] 

RS(ND(B(i))) = TooSmall [Exponent Underflow] 

NS(RS(ND(B(i)))) = TooSmall [Exponent Underflow] 

CREL 

v 95A8 See CEQD 

CVS2 

v 9554 

also partly represents CV2S 

Inv Arg/Par: x(TOS) not single integer 

Uninit Arg: x(TOS) tag in {6,4} 

CV2S 

v 9555 

Interrupts same as CVS2, plus: 

Inv Arg/Par: X(TOS) 47:3 > 0 or 38:7 > 0 

DBCD 

v 957F 

Int Overflow: RId(B) = TooBig 

Int Arg/Par: N (TOS) not operand or RaI(N) not {0 to 24} 

B (TOS2) not operand 


DBFL 

p A8 See DBUN 

DBRS 

p 9F 

also represents DBST 

Inv Arg/Par: Db (TOS) not operand or RaI(Db) not {0 to 47} 

Uninit Arg: Db tag in {6, 4} 

6878 7530–007 F–17


DBST 

p 97 See DBRS 

DBTR 

p A9 See DBUN 

DBUN 

p AA 

also represents DBFL & DBTR 

See aEIRW: evaluate SIRW 

See aPRCW: distribute branch-dest PCW code-stream pointer 

Bounds Error: (branch-dest opnd.dyn_pwi)mod 2**14 >= ActSegLen(PSN) 

Inv Arg/Par: branch-dest (TOS) not {operand, PCW, SIRW} 

(branch-dest operand) > 2**39-1 

Inv Target: SIRW >> not PCW 

Uninit Arg: branch-dest (TOS) tag in {6, 4} 

DEXI 

v 9547 No interrupts 

DFTR 

p 99 

Inv Arg/Par: Len (TOS) not operand or RaI(Len) not {0 to 48} 

Sb (TOS2) not operand or RaI(Sb) not {0 to 47} 

Db (TOS3) not operand or RaI(Db) not {0 to 47} 

Uninit Arg: Len or Sb or Db tag in {6, 4} 

DINS 

p 9D 

Inv Arg/Par: Len (TOS2) not operand or RaI(Len) not {0 to 48} 


Uninit Arg: Len or Db tag in {6, 4} 

DISO 

p 9B 

Inv Arg/Par: Len (TOS) not operand or RaI(Len) not {0 to 48} 


Uninit Arg: Len or Sb tag in {6, 4} 

DIVD 

p 83 

Arith Overflow: R(x/y) = TooBig [Exponent Overflow] 

divisor (TOS) is 0 [Divide by Zero] 

Arith Underflow: R(x/y) = TooSmall [Exponent Underflow] 

R(x/y) < > R*(x/y) [Precision Loss] 

N(R(x/y)) = TooSmall but R = R* < > 0 [spurious] 



F–18 6878 7530–007

DLET 


p B5 No interrupts 

DOT 

v 95C4 



See aFOP: fetch via current vector_A or vector_B 

See aVOAV: validate vector_A:I1DD, vector_B:I1DD, length, 

stride_A, stride_B, sum:sp operand 

Vect Arith Exc: R(A(i)*B(i)) = TooBig [Exponent Overflow] 

R(A(i)*B(i)) = TooSmall [Exponent Underflow] 

R(A(i)*B(i)) < > R*(A(i)*B(i)) [Precision Loss] 

N(R(A(i)*B(i))) = TooSmall 

but R = R* < > 0 [spurious] 

R(sum+...) = TooBig [Exponent Overflow] 

DOTX 

v 95C5 




See aVOAV: validate vector_A:IWDD, vector_B:IWDD, length, 

stride_A, stride_B, sum:dp operand 

Vect Arith Exc: R(A(i)*B(i)) = TooBig [Exponent Overflow] 






DRNT 

v 9583 

Inv Arg/Par: X (TOS3) or L (TOS2) or H (TOS) not operand 

Uninit Arg: X or L or H tag in {6, 4} 

DUPL 


EEXI 


ENDE 

te DE No interrupts 

ENDF 

te D5 & MinusChar:8 & PlusChar:8 See INSU 

6878 7530–007 F–19


ENTR 

p AB 

See aEIRW: evaluate SIRW at F+2 or successor SIRW 



Missing PCW: Stk[F+2] not {SIRW, PCW} 

SIRW >> not {SIRW, PCW} 

EQUL 

p 8C 

also represents GREQ, GRTR, LESS, LSEQ, NEQL 

Inv Arg/Par: TOS not operand or TOS2 not operand 


EVAL 

p AC 

See aACCE: SIRW >> PCW 


Inv Arg/Par: reference (TOS) not {SIRW, IDD} 


EXCH 


EXIT 

p A3 

also represents RETN & REXI, RTN2 


See aPRCW: distribute RCW code-stream pointer 

Block Exit: HISW.block_exit=1 

Structure Error: Stk[D[LL]+1] not RCW 


Stk[Histlink+1] not {entered ENVW, inactive ENVW} 

EXPU 

p DD 

See aPOAV: validate dest:pointer, length:MaxInx 

Undefined Op: next operator is ENDE, ENDF, or INSC 

next operator is MCHR, MVNU, MINS, MFLT, SFSC, or SRSC 

(which requires source) 

F–20 6878 7530–007

EXSD 

p D2 

also represents EXSU 

See aPOAV: validate dest:pointer, source:{pointer,opnd}, 

length:MaxInx 

Inv Arg/Par: source is EBCDIC and dest is hex or vice versa 

Undefined Op: next operator is ENDE, ENDF, or INSC 

EXSU 


p DA See EXSD 

EXTB (restricted) – (Libra 680 and 690 Systems) 

v 954C 

see aEIRW evaluate D[0] address couple to MEI PCW 

see aPRCW distribute MEI PCW code-stream pointer 

Missing PCW: D[0] address couple target not PCW 

FLTR 

p 98 & Db:8 & Sb:8 & Len:8 

Inv Arg/Par: Db > 47 or Sb > 47 or Len > 48 

FMN 

v 95CA 

also represents FMX, FMXA 



See aVOAV: validate vector_A:IWDD, length, stride_A, 

X:sp operand, V:operand 

Inv Arg/Par: vector_A is sp and V is dp or vice versa 

FMX 

v 95C9 See FMN 

FMXA 

v 95CB See FMN 

GASF (restricted) 


GASP (restricted) 

v 955A No interrupts 

6878 7530–007 F–21


GATH 

v 95C1 


vector_B argument by referent(vector_I) 


See aFOP: fetch via current vector_B or vector_I 


See aVOAV: validate vector_A:IWDD, vector_B:IWDD, 

length, stride_A, vector_I:I1DD 


Inv Target: current vector_I >> not single_integer 

vector_I single_integer > MaxInx 

GESZ 

v 95CF 

Inv Arg/Par: TOS not touched DD 

Uninit Arg: TOS tag in {6,4} 

GEXT (restricted) 

v 955E No interrupts 

GINX 

v 95CE 


Structure Error: ASD3 for paged indexed DD is not unpaged indexed DD 

(not checked if page index known) 


GLEN 

v 95CD 


Structure Error: unpaged or unindexed DD not ASD2 

ASD3 for paged indexed DD is not unpaged indexed DD 


paged indexed DD PageTable.ASD_ref not ASD2 


GREQ 

p 89 See EQUL 

GRTR 

p 8A See EQUL 

GSTN (restricted) 

v 955C No interrupts 

HALT (restricted) 

v 95DF No interrupts 

F–22 6878 7530–007

ICLD 


v 9575 See ICUD 

ICRD 

v 9576 See ICUD 

ICUD 

p A4 

also represents ICLD, ICRD, ICVD 

See aCHAR: access word via source ICDD 

See aPOAV: validate source:{pointer,opnd}, length:23 

ICVD 

p CA See ICUD 

IDIV 

p 84 

also partly represents RDIV 

Arith Overflow: divisor (TOS) is 0 [Divide by Zero] 

Int Overflow: x and y are sp and x DIV y >= 2**39 

x or y is dp and x DIV y >= 2**78 



IDLE (restricted) – (Libra 680 and 690 Systems) 


IMKS 

p CF No interrupts 

INDX 

p A6 

The representability interrupts associated with applying index to a DD 

are shown under aAPIX. 

See aAPIX: DD argument by RaI(index argument) 


See aEIXD: evaluate final IDD 

Bounds Error: RaI(index argument) > MaxInx 

Inv Arg/Par: not ( TOS in {CopyDD, SIRW} and 

TOS2 is operand 

or TOS is operand and 

TOS2 in {CopyDD, SIRW} ) 

TOS or TOS2 is reindex-disabled IDD 

SIRW >> reindex-disabled IDD 

Inv Target: SIRW >> not {SIRW, touched DD, untouched DD} 

Touch Reference: SIRW >> untouched DD 


6878 7530–007 F–23


INOP 

e D8 See INSG 

INSC 

te DD & Length:8 & ZeroChar:8 & NonZeroChar:8 See INSU 

INSG 

e D9 & MinusChar:8 & PlusChar:8 

also represents INOP 

Interrupts same as INSU, plus: 

Inv Arg/Par: dest is hex 

INSR 

p 9C & Db:8 & Len:8 No interrupts 

INSU 

se DC & Char:8 

te DC & Length:8 & Char:8 

also represents ENDF, INSC 

also partly represents INSG & INOP 

See aCHAR: access word via dest ICDD 

Dest Boundary: dest segment exhausted 

Inv Access: read_only destination pointer 

IPST (restricted) – (Libra 680 and 690 Systems) 


ISOL 

p 9A & Sb:8 & Len:8 No interrupts 

JOIN 

v 9542 

Inv Arg/Par: TOS not operand or TOS2 not operand 


LAND 

p 90 No interrupts 

LDNC (restricted) – (Libra 680 and 690 Systems) 

v 9594 

also represents LDNO 

Inv Arg/Par: ref (TOS) not {IDD, ASRW, sp integer} 

|sp integer| > MaxInx 


F–24 6878 7530–007


LDNO (restricted) – (Libra 680 and 690 Systems) 

v 959B See LDNC 

LEQV 


LESS 

p 88 See EQUL 

LNMC 

v 958C & lambda:4 & delta:12 See NAMC 

LNOT 


LOAD 

p BD 

See aFOP: fetch via SIRW or IDD 

Inv Arg/Par: reference (TOS) not {SIRW, IDD} 

Inv Target: SIRW or I1DD or ICDD >> not {SIRW, DD, Data Word} 

Touch Load: SIRW or I1DD or ICDD >> untouched DD 


LODC 

p FD 

See aEIXD: evaluate IDD 

Inv Arg/Par: TOS not IDD 

Inv Target: IDD >> not operand 


LODT 

p BC 

v 95BC 



Bounds Error: |sp integer| not > MaxInx, but 

sp integer < 0 or > 2**36-1 (Libra 680 and 690 systems) 

sp integer < 0 or > 2**32-1 (Libra 4000 systems) 

Inv Arg/Par: ref (TOS) not {SIRW, IDD, ASRW, sp integer} 



LOG2 

v 958B No interrupts 

6878 7530–007 F–25


LOR 


LSEQ 

p 8B See EQUL 

LT8 

p B2 & constant:8 No interrupts 

LT16 

p B3 & constant:16 No interrupts 

LT48 

p BE & word-aligned constant:48 No interrupts 

LVLC 

v 958D & lambda:4 & delta:12 See VALC 

MCHR 

se D7 

te D7 & Length:8 

also represents MFLT, MINS, MVNU 

See aCHAR: access word via source or dest ICDD 



Source Boundary: source segment exhausted 

MFLT 

se D1 & ZeroChar:8 & MinusChar:8 & PlusChar:8 

te D1 & Length:8 & ZeroChar:8 & MinusChar:8 & PlusChar:8 See MCHR 

MINS 

se D0 & ZeroChar:8 

te D0 & Length:8 & ZeroChar:8 See MCHR 

MKSN 

p DF No interrupts 

MKST 

p AE No interrupts 

MPCW 

p BF & word-aligned SkeletonPCW:48 

See aEAC: evaluate (sdll,sdi) from parameter 

Inv Target: (sdll,sdi) >> not {CSD, untouched CSD} 

Touch CSD: (sdll,sdi) >> untouched CSD 

F–26 6878 7530–007

MPWL 

p F6 

also represents MPWP 



Inv Arg/Par: TOS not in {SIRW, IDD} 

Inv Target: SIRW or IDD >> not {CSD, untouched CSD} 

Touch CSD: SIRW or IDD >> untouched CSD 

MPWP 


p F7 See MPWL 

MULT 

p 82 

also represents MULX 

Arith Overflow: R(x*y) = TooBig [Exponent Overflow] 

Arith Underflow: R(x*y) = TooSmall [Exponent Underflow] 

R(x*y) < > R*(x*y) [Precision Loss] 

N(R(x*y)) = TooSmall but R = R* < > 0 [spurious] 



MULX 

p 8F See MULT 

MVNU 

se D6 

te D6 & Length:8 See MCHR 

MVST (restricted) 

v 95AF 


Super Halt: stack-number > not ASD1/ASD2 

destination Stk[0] not TSCW 

NAMC 

p 01:2 & variable-fence address couple:14 (two syllables total) 

No interrupts 

NEQL 

p 8D See EQUL 

NMC0 

p C4 & delta:16 No interrupts 

NMC1 


6878 7530–007 F–27


NMC2 


NMC3 


NOOP 

p FE 

v 95FE No interrupts 

NORM 

v 958E 

Arith Overflow: N(x) = TooSmall [Exponent Underflow] 

Inv Arg/Par: x (TOS) not operand 


NORX 

v 957C 

Inv Arg/Par: TOS not indexed DD 


NOWR 

v 957D 



NTGD 

v 9587 

Int Overflow: RId(x) = TooBig 



NTGR 

p 87 

Int Overflow: RaI(x) = TooBig 



NTIA 

p 86 

Int Overflow: TI(x) = TooBig 



F–28 6878 7530–007

NTTD 

v 9586 

Int Overflow: TId(x) = TooBig 



NVLD 

p FF 

v 95FF 

Invalid Operator: (unconditional) 

NXLN 

p A5 



See aEIXD: evaluate final IDD 








Inv Target: SIRW >> not {SIRW, touchedDD, untouched DD} 

DD[index argument] >> not {untouched DD, 

unindexed DD} 

Touch Load: DD[index argument] >> untouched DD 



NXLV 

p AD 



See aFOP: fetch via final indexed DD 








Inv Target: SIRW >> not {SIRW, touchedDD, untouched DD} 




6878 7530–007 F–29


OCRX 

v 9585 

Bounds Error: RaI(index argument) not {1 to ICW.ICW_limit} 

Inv Arg/Par: ICW (TOS) not sp opnd or index (TOS2) not opnd 


ONE 


OVRD 

p BA 

also represents LCEX, OVRN, and RDLK 




Inv Arg/Par: reference (TOS) not {SIRW, IDD, ASRW} 

Inv Address: if address is greater than 2**32-1 (Libra 4000 systems) 

Uninit Arg: reference tag in {6, 4} 

OVRN 

p BB See OVRD 


PAUS (restricted) – (Libra 680 and 690 Systems) 


PKLD 

v 9573 See PKUD 

PKRD 

v 9574 See PKUD 

PKUD 

v 9572 

also represents PACD, PKLD, PKRD 


See aPOAV: validate source:{pointer,opnd}, length:24 

F–30 6878 7530–007

POLY 

v 95C7 




See aVOAV: validate vector_A:IWDD, vector_B:{IWDD,opnd}, 



Inv Arg/Par: vector_A or vector_B is dp and Z is sp 

Vect Arith Exc: R(B(i)*Z) = TooBig [Exponent Overflow] 

R(B(i)*Z) = TooSmall [Exponent Underflow] 

R(B(i)*Z) < > R*(B(i)*Z) [Precision Loss] 

N(R(B(i)*Z)) = TooSmall 


R(A(i)+...) = TooBig [Exponent Overflow] 

PUSH 


RASD (restricted) 

v 95B1 

also represents WASD 

Inv Arg/Par: specifier (TOS) not sp integer < MaxInx 

ASD_num (TOS2) not sp integer < MaxInx 


RCMT (restricted) – (Libra 

680 and 690 Systems) 

v 956B No interrupts 

RDIV 

p 85 

Interrupts same as IDIV, plus: 

Arith Underflow: N(x MOD y) = TooSmall [spurious] 

RDLK 

v 95BA See OVRD 

RDMT (restricted) – (Libra 680 and 690 

Systems) 

v 956A No interrupts 

6878 7530–007 F–31


REMW (restricted) – (Libra 680 and 690 

Systems) 

v 9565 

See aAPIX: source UDD by (source index)/2 

See aEIXD: evaluate final indexed source DD 

Inv Arg/Par: source UDD not in {SIRW, DD} 

source index not sp integer 

|source sp integer| > MaxInx 

Uninit Arg: any argument tag in {6, 4} 

RETN 

p A7 See EXIT 

REXI (restricted) 

v 95F7 See EXIT 

RIPS (restricted) 


RIRR (restricted) – (Libra 680 and 690 

Systems) 


RMTR (restricted) 


ROFF 

p D7 No interrupts 

RPRR (restricted) 

v 95B8 

also represents RREG, WREG 

Inv Arg/Par: reg-id (TOS) not operand 


RREG (restricted) – (Libra 680 and 690 Systems) 

v 9561 See RPRR 

RSDN 

v 95B7 No interrupts 

RSNR 


F–32 6878 7530–007

RSQR 

v 9550 

Inv Arg/Par: x (TOS) not operand or x < 0 


RSTF 


e D4 No interrupts 

RSUP 


RTAG 


RTFF 

p DE No interrupts 

RTN2 

v 95AE See EXIT 

RTOD 

v 95A7 No interrupts 

RUNI (restricted) – (Libra 680 and 690 Systems) 


SAME 


SASF (restricted) 

v 9559 

also represents SASP, SSTN 



SASP (restricted) 

v 955B See SASF 

6878 7530–007 F–33


SCAT 

v 95C0 

See aAPIX: vector_A argument by referent(vector_I) 



See aFOP: fetch via current vector_B or vector_I 



length, vector_I:I1DD, stride_B 


Inv Target: current vector_I >> not single_integer 


SCMP 

v 95AA See CEQD 

SCPY 

v 95AB See TEQD 

SCRD (restricted) – (Libra 680 and 690 Systems) 


SEDW 

v 95A3 See SESW 

SEQ 

v 95C6 







Inv Arg/Par: vector_A is sp and vector_B is dp 

vector_A is sp and Z is dp or vice versa 

Vect Arith Exc: R(Z+B(i)) = TooBig [Exponent Overflow] 

SEQD 

v 95F4 

also represents SEQU, SGED, SGEU, SGTD, SGTU, SLED, 

SLEU, SLSD, SLSU, SNED, SNEU 


See aPOAV: validate source:{pointer,opnd}, 


SEQU 

v 95FC See SEQD 

F–34 6878 7530–007

SESW 

v 95A2 

also represents SEDW 


See aAPIX: argument pointer by 0 (after element_size change) 

Inv Arg/Par: TOS not copyDD 

pointer reindex disabled 

Uninit Arg: TOS in tag {6, 4} 

SEXT (restricted) 

v 955F No interrupts 

SE4C 

v 95A0 See SE8C 

SE8C 

v 95A1 

also represents SE4C 

See aAPIX: argument pointer by 0 (after element_size change) 

Bounds Error: IWDD.index >= 2**16 (implied by aAPIX) 

Inv Arg/Par: TOS not copyDD 



SFDC 

se DA 

te DA & Length:8 

See aAPIX: current dest ICDD by +max(length,0) 

aAPIX errors caused by new index not reported by EXSD SFDC. 

SFSC 

se D2 


See aAPIX: current source ICDD by +max(length,0) 


SGED 

v 95F1 See SEQD 

SGEU 


SGTD 


6878 7530–007 F–35


SGTU 

v 95FA See SEQD 

SINT – (Libra 680 and 690 Systems) (restricted) 

v 9545 


NTGR (TOS) result not 11-bit integer 


SISO 

p D5 



length:(if source is hex then 24 else 12) 

SLED 


SLEU 

v 95FB See SEQD 

SLSD 


SLSU 


SNED 


SNEU 

v 95FD See SEQD 

SNGL 

p CD 

Arith Overflow: RS(ND(x)) = TooBig [Exponent Overflow] 

Arith Underflow: RS(ND(x)) = TooSmall [Exponent Underflow] 

NS(RS(ND(x))) = TooSmall [Exponent Underflow] 



F–36 6878 7530–007

SNGT 

p CC 

See aAPIX: IDD argument by 0 


Arith Overflow: TS(ND(x)) = TooBig [Exponent Overflow] 

Arith Underflow: TS(ND(x)) = TooSmall [Exponent Underflow] 

NS(TS(ND(x))) = TooSmall [Exponent Underflow] 

Inv Arg/Par: x (TOS) not {operand, copyDD} 

IDD reindex disabled 


SPLT 

v 9543 



SPRR (restricted) 

v 95B9 

Inv Arg/Par: reg-val (TOS) not operand 

reg-id (TOS2) not operand 


SRCH 

v 95BE 

It is convenient to define SRCH as a variant of BMS in which the length 

argument is implicitly one more than the initial virtual index of the 

domain argument. The domain is exhausted when the length is counted to 

zero. 

See aAPIX: current domain by -1 

See aEIXD: evaluate current domain 

Inv Arg/Par: domain (TOS) not I1DD 


Uninit Arg: domain tag in {6, 4} 

SRDC 

se DB 

te DB & Length:8 

See aAPIX: current dest ICDD by -max(length,0) 


SRSC 

se D3 


See aAPIX: current source ICDD by -max(length,0) 


6878 7530–007 F–37


SSTN (restricted) 

v 955D See SASF 

STAG 

v 95B4 

Inv Arg/Par: tag value (TOS) not operand 


STCD 

p F8 

also represents STCN 



Inv Arg/Par: not ( TOS is IDD and TOS2 is operand 

or TOS is sp operand and TOS2 is IDD) 

Inv Target: IDD >> not operand 


STCN 

p F9 See STCD 

STFF 

p AF No interrupts 

STOD 

p B8 

also represents STON 

See aACCE: SIRW >> PCW 


See aSOP: store via SIRW or IDD 

Inv Arg/Par: not ( TOS in {SIRW, IDD} and TOS2 is operand 

or TOS is operand and TOS2 in {SIRW, IDD} ) 

Inv Target: SIRW >> not {SIRW, IDD, PCW, untouched DD, 

Data Word} 



STON 

p B9 See STOD 

STOP (restricted) 

v 95BF No interrupts 

F–38 6878 7530–007

SUBT 

p 81 


Arith Overflow: R(x-y) = TooBig [Exponent Overflow] 



SUM 

v 95C2 

also represents SUMA 



See aVOAV: validate vector_A:IWDD, length, stride_A, 

sum:operand 

Inv Arg/Par: current vector_A is dp and sum is sp 

Vect Arith Exc: R(sum+A(i)) = TooBig [Exponent Overflow] 

SUMA 

v 95C3 See SUM 

SUMW 

v 95CC 



See aVOAV: validate vector_A:I1DD, length, stride_A, SUM:operand 

SWFD 

v 95D4 

also represents SWFU, SWTD, SWTU 

See aAPIX: set by WordIndex(c) 


See aEIXD: evaluate set[WordIndex(c)], if length > 0 



Inv Target: set[WordIndex(c)] >> not operand 

SWFU 

v 95DC See SWFD 

SWTD 

v 95D5 See SWFD 

SWTU 

v 95DD See SWFD 

6878 7530–007 F–39


SXSN 

p D6 



TEED 

p D0 

also represents TEEU 


edtab: unpaged indexed DD 

Absent Data: edtab 

Bounds Error: edtab.ewi >= ActSegLen(table) 

edtab.esi > 5 


Structure Error: edtab not ASD1/ASD2 

TEEU 

p D8 See TEED 

TEQD 

p E4 

also represents TEQU, TGED, TGEU, TGTD, TGTU, TLED, 

TLEU, TLSD, TLSU, TNED, TNEU, SCPY 







Source Boundary: source element exhausted 

TEQU 

p EC See TEQD 

TGED 

p E1 See TEQD 

TGEU 

p E9 See TEQD 

TGTD 

p E2 See TEQD 

TGTU 

p EA See TEQD 

F–40 6878 7530–007

TLED 


p E3 See TEQD 

TLEU 

p EB See TEQD 

TLSD 

p E0 See TEQD 

TLSU 

p E8 See TEQD 

TNED 

p E5 See TEQD 

TNEU 

p ED See TEQD 

TRNS 

v 95D7 

See aAPIX: trtab by WordIndex(c) 


See aEIXD: evaluate trtab[WordIndex(c)], if length > 0 


length:MaxInx, trtab:I1DD 



Inv Target: trtab[WordIndex(c)] >> not operand 


TUND 

p E6 

also represents TUNU 



length:MaxInx 





TUNU 

p EE See TUND 

6878 7530–007 F–41


TWFD 

v 95D2 

also represents TWFU, TWTD, TWTU 

See aAPIX: set by WordIndex(c) 


See aEIXD: evaluate set[WordIndex(c)], if length > 0 






Inv Target: set[WordIndex(c)] >> not operand 


TWFU 

v 95DA See TWFD 

TWOD (restricted) 

p D4 

See aAPIX: current source or dest pointer (as I1DD) by +1 

See aEIXD: evaluate current source or dest pointer, if length > 0 

See aPOAV: validate dest:{pointer,ASRW}, 

source:{pointer,ASRW,opnd}, 

length:MaxInx 



TWSD 

p D3 

also represents TWSU 

See aAPIX: current source or dest pointer (as I1DD) by +1 

See aEIXD: evaluate current source or dest pointer, if length > 0 


length:MaxInx 



Inv Target: source pointer >> not operand 


TWSU 

p DB See TWSD 

TWTD 

v 95D3 See TWFD 

TWTU 

v 95DB See TWFD 

F–42 6878 7530–007

UPLD 


v 9570 See UPUD 

UPLU 


UPRD 


UPRU 


UPUD 

v 95D1 

also represents UPLD, UPLU, UPRD, UPRU, UPUU, USND, USNU 

See aCHAR: access word via dest ICDD 

See aPOAV: validate dest:pointer, source:operand, length:MaxInx 



UPUU 

v 95D9 See UPUD 

USND 


USNU 


VALC 

p 00:2 & variable-fence address couple:14 (two syllables total) 

also represents LVLC, VLCO, VLC1, VLC2, VLC3 

See aACCE: parameter or SIRW >> PCW 

See aFOP: fetch via parameter or subsequent reference 

Inv Arg/Par: restart TOS not {SIRW, IDD, operand} 

Inv Target: parameter or SIRW >> 

not {SIRW, IDD, PCW, untouched DD, opnd} 

Touch Reference: parameter or SIRW >> untouched DD 

VARI 


VLC0 

p C0 & delta:16 See VALC 

6878 7530–007 F–43


VLC1 


VLC2 


VLC3 


VMV 

v 95E6 








Vect Arith Exc: R(A(i)-B(i)) = TooBig [Exponent Overflow] 

VMVN 

v 95E7 








Vect Arith Exc: R(B(i)-A(i)) = TooBig [Exponent Overflow] 

VOV 

v 95E9 








Vect Arith Exc: R(A(i)/B(i)) = TooBig [Exponent Overflow] 

R(A(i)/B(i)) = TooSmall [Exponent Underflow] 

R(A(i)/B(i)) < > R*(A(i)/B(i)) [Precision Loss] 

N(R(A(i)/B(i))) = TooSmall 


B(i) is 0 [Divide by Zero] 

F–44 6878 7530–007

VPS 

v 95EB 









vector_A is sp and S is dp or vice versa 

Vect Arith Exc: R(B(i)+S) = TooBig [Exponent Overflow] 

VPV 

v 95E5 








Vect Arith Exc: R(A(i)+B(i)) = TooBig [Exponent Overflow] 

VPVS 

v 95ED 









Vect Arith Exc: R(B(i)*S) = TooBig [Exponent Overflow] 

R(B(i)*S) = TooSmall [Exponent Underflow] 

R(B(i)*S) < > R*(B(i)*S) [Precision Loss] 

N(R(B(i)*S)) = TooSmall 



6878 7530–007 F–45


VSPV 

v 95EE 





See aVOAV: validate vector_A:IWDD, vector_B:{IWDD,opnd} 




Vect Arith Exc: R(A(i)*S) = TooBig [Exponent Overflow] 

R(A(i)*S) = TooSmall [Exponent Underflow] 

R(A(i)*S) < > R*(A(i)*S) [Precision Loss] 

N(R(A(i)*S)) = TooSmall 


R(...+B(i)) = TooBig [Exponent Overflow] 

VTS 

v 95EC 









Vect Arith Exc: R(B(i)*S) = TooBig [Exponent Overflow] 


R(B(i)*S) < > R*(B(I)*S) [Precision Loss] 



VTV 

v 95E8 








Vect Arith Exc: R(B(i)*A(i)) = TooBig [Exponent Overflow] 

R(B(i)*A(i)) = TooSmall [Exponent Underflow] 

R(B(i)*A(i)) < > R*(B(i)*A(i)) [Precision Loss] 

N(R(B(i)*A(i))) = TooSmall 


F–46 6878 7530–007

VUV 

v 95EA 









Vect Arith Exc: R(B(i)/A(i)) = TooBig [Exponent Overflow] 

R(B(i)/A(i)) = TooSmall [Exponent Underflow] 

R(B(i)/A(i)) < > R*(B(i)/A(i)) [Precision Loss] 

N(R(B(i)/A(i))) = TooSmall 


A(i) is 0 [Divide by Zero] 

WASD (restricted) 

v 95B3 See RASD 

WATI (restricted) 

v 95A4 No interrupts 

WEMW (restricted) – (Libra 680 and 690 

Systems) 

v 9566 

See aAPIX: dest UDD by (dest index)/2 

See aEIXD: evaluate final indexed dest DD 

Inv Access: read_only dest UDD 

Inv Arg/Par: dest UDD not in {SIRW, DD} 

dest index not sp integer 

|dest sp integer| > MaxInx 

Uninit Arg: any argument tag in {6, 4} 

WHOI (restricted) 

v 954E No interrupts 

WIPS (restricted) 

v 9599 

Undefined Op: state identifier 5:1 true (N68xx code) 

WMTR (restricted) 

v 9569 

Inv Arg/Par: timer value not operand 

WREG (restricted) – (Libra 680 and 690 Systems) 

v 9562 See RPRR 

6878 7530–007 F–47


WTOD (restricted) 

v 9549 

Structure Error: TOS not operand 

XTND 

p CE 

See aAPIX: IDD argument by 0 

Inv Arg/Par: TOS not {operand, copyDD} 



ZERO 


ZIC (restricted) 


F–48 6878 7530–007

Appendix G 

Interupt Reference 

This appendix lists each interrupt in alphabetical order of the interrupt name. The 

condition group (CVI or OVI) is shown for each interrupt. The offset is shown for each 

OVI. The characterization as operator-dependent (ODI) or spontaneous (SI) is also shown. 

The common actions and operators that invoke each ODI are listed alphabetically along 

with an indication of the reason for the invocation. The same notation and conventions 

are used as in Appendix F. 

Absent Code Segment CVI 4 (04) ODI 

The interrupt condition is ASD1.present_to_proc = 0 in the ASD designated by the object 

indicated. 

aPRCW: PCW or RCW 

Absent Data Segment CVI 3 (03) ODI 

The interrupt condition is ASD1.present_to_proc = 0 in the ASD designated by the object 

indicated. 

aAPIX: client paged unindexed DD (page table) 


aEIXD: client indexed DD 


aEVLK: if pseudolink = 0: 

ASD1[stack_num].present_to_proc = 0 


ASD1[seg_num].present_to_proc = 0 

CHES ASD1[PCW.ASD_ref].present_to_proc = 0 

TEED & TEEU: edtab 

6878 7530–007 G–1


Arithmetic Overflow OVI 0 ODI 

The arithmetic exception condition reported to software (defined in Section 4) is named 

in brackets following the arithmetic situation that causes the interrupt. 

ADD: R(x+y) = TooBig [Exponent Overflow] 

DIVD: R(x/y) = TooBig [Exponent Overflow] 

divisor (TOS) is 0 [Divide by Zero] 

IDIV & RDIV: divisor (TOS) is 0 [Divide by Zero] 

MULT & MULX: R(x*y) = TooBig [Exponent Overflow] 

SNGL: RS(ND(x)) = TooBig [Exponent Overflow] 

SNGT: TS(ND(x)) = TooBig [Exponent Overflow] 

SUBT: R(x-y) = TooBig [Exponent Overflow] 

Arithmetic Underflow OVI 1 ODI 

The arithmetic exception condition reported to software (defined in Section 4) is named 

in brackets following the arithmetic situation that causes the interrupt. The processor 

generates interrupts for a subset of those situations labeled "spurious." 

DIVD: R(x/y) = TooSmall [Exponent Underflow] 

R(x/y) < > R*(x/y) [Precision Loss] 

N(R(x/y)) = TooSmall but R = R* < > 0 [spurious] 

MULT & MULX: R(x*y) = TooSmall [Exponent Underflow] 

R(x*y) < > R*(x*y) [Precision Loss] 

N(R(x*y)) = TooSmall but R = R* < > 0 [spurious] 

NORM: N(x) = TooSmall [Exponent Underflow] 

RDIV: N(x MOD y) = TooSmall [spurious] 

SNGL: N(x) = TooSmall [Exponent Underflow] 

RS(ND(x)) = TooSmall [Exponent Underflow] 

NS(RS(ND(x))) = TooSmall [Exponent Underflow] 

SNGT: N(x) = TooSmall [Exponent Underflow] 

TS(ND(x)) = TooSmall [Exponent Underflow] 

NS(TS(ND(x))) = TooSmall [Exponent Underflow] 

Block Exit CVI 11 (0B) ODI 

EXIT etc.: HISW.block_exit=1 

G–2 6878 7530–007

Bounds Error CVI 18 (12) ODI 

aAPIX: The following conditions detected by aAPIX cause 

client to generate interrupt if resulting 

(unrepresentable) DD is used or returned: 

new virtual index < 0 

unpaged DD and new index >= 2**20 

unpaged CharDD and new word index >= 2**16 

new page index >= ActSegLen(PageTable) 

aEIRW: displacement+offset >= ActSegLen 

aEIXD: word index >= ActSegLen 

(except when ultimate client can generate 

Source or Destination Boundary interrupt) 

page index >= ActSegLen (Page Table) 

aEVLK: displacement >= ActSegLen 

aPOAV: for client source or destination pointer 

(blocked by zero-length operator that deletes 

its arguments) 

IWDD.index > ActSegLen 

ICDD.word_index > ActSegLen 

ICDD.word_index = ActSegLen and .char_index > 0 

IWDD.index >= 2**16 

and client is not Transfer Words 

aPRCW: (PCW or RCW).pwi >= ActSegLen 

(PCW or RCW).psi > 5 

BRUN etc.: op_pwi >= ActSegLen(PSN) 

op_psi > 5 

CHES: PCW ASD2.AS_length < 2**13 

DBUN etc.: (branch-dest opnd.dyn_pwi)mod 2**14 >= 

ActSegLen(PSN) 

INDX, 

NXLN, & NXLV: RAI(index argument) > MaxInx 

OCRX: RaI(index argument) not {1 to ICW.ICW_limit} 

SE8C & SE4C: IWDD.index >= 2**16 (implied by aAPIX) 

TEED & TEEU: edtab.ewi >= ActSegLen(table) 

edtab.esi > 5 

TWSU: updated source or destination ICDD has word_index 

>= 2**16 


A Bounds Error interrupt is also generated when code execution runs off the end of the 

code or edit-table segment. The latter case is reported as an ODI on the enter-table-edit 

operator and the former case might appear as an ODI on VARI or on the first syllable of a 

polysyllabic primary operator, but in general the situation cannot be related to a particular 

operator. Note also that the error will be reported only when the code stream execution 

crosses the segment boundary, not for any anticipatory code fetch. 

Destination Boundary CVI 8 (08) ODI 

The Destination Boundary condition is that the destination pointer designates the last+1 

element of the destination sequence. For the relevent operators, this interrupt takes 

precedence over a Bounds Error interrupt (via aEIXD) on the destination pointer. 

INSU etc., MCHR etc., SCPY & TEQD etc., TRNS, 

TUND & TUNU, TWFD etc., TWSD & TWSU, 

UPUD etc.: dest segment exhausted 

6878 7530–007 G–3


Emulation Consistency Error CVI 45 (2D) SI 

Emulation Error - Here CVI 28 (1C) SI 

Emulation Error - Lost CVI 29 (1D) SI 

External Memory Write Error CVI 25 (19) SI 

False Assertion OVI 0 ODI 

AVER & ASRT: Boolean (TOS) is False 

Hardware Error - Here CVI 42 (2A) SI 

Hardware Error - Lost CVI 37 (25) SI 

Integer Overflow OVI 2 ODI 

BCD,DBCD: RId(B) = TooBig 

IDIV & RDIV: x and y are sp and x DIV y >= 2**39 

x or y is dp and x DIV y >= 2**78 

NTGD: RId(x) = TooBig 

NTGR: RaI(x) = TooBig 

NTIA: TI(x) = TooBig 

NTTD: TId(x) = TooBig 

Interval Timer CVI 44 (2C) SI 

Invalid Access CVI 22 (16) ODI 

aSOP: read_only IDD 

INSU etc., 

MCHR etc.: read_only destination pointer 

OVRD etc. read_only I1DD 

SCPY: read_only destination pointer 

STCD & STCN: read_only IDD 

TEQD etc., TRNS, TUND & TUNU, TWFD etc., TWOD, TWSD & TWSU, 

UPUD etc.: read_only destination pointer 

WEMW: read_only destination UDD 

G–4 6878 7530–007

Invalid Address - Here CVI 15 (0F) SI 

Invalid Address - Lost CVI 32 (20) SI 

Invalid Argument or Parameter CVI 17 (11) ODI 


Checks on code parameters are so marked; all other checks are on stack arguments. 

If the criterion for an Uninitialized Argument interrupt holds, that interrupt takes 

precedence over this one. 

aPOAV: client length not operand or RaI(length) > limit 


reindex disabled in client indexed DD 

(source, dest, set, trtab, or edtab) 

aSOP: object is sp and reference is I2DD 

object is sp and SIRW -->> dp opnd 

object is dp and reference is I1DD or ICDD 

object is dp and SIRW -->> {sp opnd, tag-6 word, tag-4 word} 

aVOAV: client length not sp integer or length > MaxInx 

client stride not sp integer 

or stride > MaxInx 

(client stride) * (restart count) > MaxInx 


client vector IWDD reindex disabled 

ADD, AMAX & AMIN: x (TOS2) not operand or y (TOS) not operand 

BAFP: TOS not IDD 

BCD: B (TOS) not operand 

BMS: length (TOS) not operand or RaI(length) > MaxInx 

domain (TOS2) not I1DD 


CBON: TOS not operand 

CEQD etc., 

CREL & SCMP: source1 is EBCDIC and source2 is hex or vice versa 

CHES: TOS not PCW 

CHSN etc.: TOS not operand 

CPV etc.: vector_A is sp and vector_B is dp or vice versa 

CVS2 & CV2S: x(TOS) not single integer 

DBCD: N(TOS) not operand or RaI(N) not {0 to 24} 

B(TOS2) not operand 

DBRS & DBST: Db (TOS) not operand or RaI(Db) not {0 to 47} 

DBUN etc.: branch-dest (TOS) not {operand, PCW, SIRW} 

(branch-dest operand) > 2**39-1 

DFTR: Len (TOS) not operand or RaI(Len) not {0 to 48} 



DINS: Len (TOS2) not operand or RaI(Len) not {0 to 48} 


DISO: Len (TOS) not operand or RaI(Len) not {0 to 48} 


DIVD: x (TOS2) not operand or y (TOS) not operand 

DRNT: X (TOS3) or L (TOS2) or H (TOS) not operand 

EQUL etc.: TOS not operand or TOS2 not operand 

EVAL: reference (TOS) not {SIRW, IDD} 

EXSD & EXSU: source is EBCDIC and dest is hex or vice versa 

FLTR: Db > 47 or Sb > 47 or Len > 48 

FMN etc.: vector_A is sp and V is dp or vice versa 

GATH: vector_A is sp and vector_B is dp or vice versa 

GESZ, GINX, & GLEN: TOS not touched DD 

6878 7530–007 G–5


IDIV & RDIV: x (TOS2) not operand or y (TOS) not operand 

INDX: not ( TOS in {copy DD, SIRW} and 



TOS2 in {copy DD, SIRW} ) 



INSG & INOP: dest is hex 

JOIN: TOS is not operand or TOS2 not operand 

LDNC & LNDO: reference (TOS) not {IDD, ASRW, sp integer} 


LOAD: reference (TOS) not {SIRW, IDD} 

LODC: TOS not IDD 

LODT: reference (TOS) not {SIRW, IDD, ASRW, sp integer} 


MPWL & MPWP: reference (TOS) not {IRW, IDD} 

MULT & MULX: x (TOS2) not operand or y (TOS) not operand 

NORM: x (TOS) not operand 

NORX: TOS not indexed DD 

NOWR: TOS not touched DD 

NTGD, 

NTGR, NTIA, NTTD: x (TOS) not operand 

NXLN & NXLV: not ( TOS in {copy DD, SIRW} and 



TOS2 in {copy DD, SIRW} ) 



OCRX: ICW (TOS) not sp opnd or index (TOS2) not opnd 

OVRD etc.: reference (TOS) not {SIRW, IDD, ASRW} 

POLY: vector_A or vector_B is dp and Z is sp 

RASD etc.: specifier (TOS) not sp integer < MaxInx 

ASD_num (TOS2) not sp integer < MaxInx 

REMW: source UDD not in {SIRW, DD} 

source index not sp integer 

|source sp integer| > MaxInx 

RPRR etc.: reg-id (TOS) not operand 

RSQR: x (TOS) not operand or x < 0 

SASF etc.: TOS not operand 

SCAT: vector_A is sp and vector_B is dp or vice versa 

SCPY: source is EBCDIC and dest is hex or vice versa 

SEQ: vector_A is sp and vector_B is dp 

vector_A is sp and Z is dp or vice versa 

SESW & SEDW: TOS not copy DD 


SE8C & SE4C: TOS not copy DD 


SINT: TOS not operand 

NTGR (TOS) result not 11-bit integer 

SNGL: x (TOS) not operand 

SNGT: x (TOS) not {operand, copy DD} 

IWDD reindex disabled 

SPLT: TOS not operand 

SPRR: reg-val (TOS) not operand 

reg-id (TOS2) not operand 

SRCH: domain (TOS) not I1DD 


STAG: tag value (TOS) not operand 

STCD & STCN: not ( TOS is IDD and TOS2 is sp operand 

or TOS is sp operand and TOS2 is IDD ) 

STOD & STON: not ( TOS in {SIRW, IDD} and TOS2 is operand 

G–6 6878 7530–007

or TOS is operand and TOS2 in {SIRW, IDD} ) 

SUBT: x (TOS2) not operand or y (TOS) not operand 

SUM & SUMA: vector_A is sp and sum is dp 

SXSN: TOS not operand 

TEED & TEEU: source is EBCDIC and dest is hex or vice versa 

TEQD etc., TUND & TUNU, 

TWFD etc.: source is EBCDIC and dest is hex or vice versa 

VALC etc.: restart TOS not {SIRW, IWDD, operand} 

VMV, VMVN, VOV: vector_A is sp and vector_B is dp 

VPS: vector_A is sp and vector_B is dp 


VPV: vector_A is sp and vector_B is dp 

VPVS, VSPV, VTS: vector_A is sp and vector_B is dp 


VTV, VUV: vector_A is sp and vector_B is dp 

WEMW: dest index not in {SIRW, DD} 

dest index not sp integer 

|dest sp integer| > MaxInx 

WMTR: timer value (TOS) not operand 

WTOD: TOS is not 36-bit integer 

XTND: TOS not {operand, copy DD} 


Invalid Code Word CVI 35 (23) SI 

Invalid Operator CVI 21 (15) ODI 

NVLD: (unconditional) 


6878 7530–007 G–7


Invalid Target CVI 14 (OE) ODI 

aCHAR: client dest ICDD >> not operand 

client source ICDD >> not operand 

aFOP: 2nd word via SIRW or address couple 

not operand 

I1DD >> not operand (except for LOAD) 

I2DD >> not operand 

ICDD >> not operand (except for LOAD) 

2nd word via I2DD not operand 

aSOP: IWDD >> not Data Word (not checked for STOD & STON) 

2nd word not Data Word (not checked for STOD & STON) 

DBUN etc.: SIRW >> not PCW 

GATH: current vector_I >> not single_integer 


INDX: SIRW >> not {SIRW, touched DD, untouched DD} 

LOAD: SIRW or ICDD >> not {SIRW, DD, Data Word} 

LODC: IDD >> not operand 

MPCW: (sdll,sdi) >> not {CSD, untouched CSD} 

MPWL & MPWP: SIRW or IDD >> not {CSD, untouched CSD} 

NXLN: SIRW >> not {SIRW, touched DD, untouched DD} 

DD[index argument] >> not {untouched DD, unindexed DD} 

NXLV: SIRW >> not {SIRW, touched DD, untouched DD} 

SCAT: current vector_I >> not single_integer 


STCD & STCN: IDD >> not operand 

STOD & STON: SIRW >> not {SIRW, IWDD, PCW, untouched DD, Data Word} 

SWFD etc.: set [WordIndex(c)] >> not operand 

TRNS: trtab[WordIndex(c)] >> not operand 

TWFD etc.: set[WordIndex(c)] >> not operand 

TWSD & TWSU: source pointer >> not operand 

VALC etc.: address couple or SIRW >> not {SIRW, IDD, PCW, untouched DD, opnd} 

Loop Timer - Here CVI 41 (29) SI 

Loop Timer - Lost CVI 36 (24) SI 

Memory Data Error - Here CVI 30 (1E) SI 

Memory Data Error - Lost CVI 16 (10) SI 

Missing PCW CVI 2 (02) ODI 

aINTE: SIRW >> not {SIRW, PCW} 

ENTR: Stk[F+1] not {SIRW, PCW} 

SIRW >> not {SIRW, PCW} 

EXTB: D[0] address couple target not PCW 

G–8 6878 7530–007

Non-maskable External CVI 27 (1B) SI 

Running Timeout CVI 40 (28) SI 

SLC Interface Error - Here CVI 31 (1F) SI 

SLC Interface Error - Lost CVI 39 (27) SI 

Source Boundary CVI 9 (09) ODI 


The Source Boundary condition is that the source pointer designates the last+1 element 

of the source sequence for a pointer operator that transfers data from a source to a 

destination. For the relevant operators, this interrupt takes precedence over a Bounds 

Error interrupt (via aEIXD) on the source pointer. 

MCHR etc., 

SCPY, 

TEQD etc., 

TRNS, 

TUND & TUNU, 

TWFD etc., 

TWSD & TWSU: source segment exhausted 

Stack Overflow CVI 33 (21) SI 

Stack Overflow, while caused by operator action, is defined as a spontaneous interrupt. 

Any operator that produces more words of stack output than it consumes as stack 

arguments increases the size of the expression stack. The actual interrupt generation 

may occur because of an operator like PUSH or ENTR that has no net effect on the size 

of the stack, but forces expressionstack values to migrate from processor registers to 

the stack in memory. 

Stack Underflow CVI 34 (22) SI 

Stack Underflow interrupts can be generated by or on behalf of any operator that 

consumes one or more arguments from the top of the stack. These situations are not 

listed as operator-dependent interrupts; they are considered spontaneous interrupts 

generated by the stack-adjust mechanism. 

6878 7530–007 G–9


Structure Error CVI 20 (14) ODI 

aAPIX: ASD3 for paged indexed DD is not unpaged indexedDD 



paged unindexed DD > not ASD1/ASD2 (page table) 

PageTable[new page index] 

not {unpaged unindexed DD, untouched DD} 

aEIXD: client indexed DD > not ASD1/ASD2 

ASD3 for paged indexed DD is not unpaged indexedDD 



PageTable[page index] not {unpaged unindexed DD, 

untouched DD} 

aEVCH: for each AR traversed on environmental chain: 

MSCW.env_link or D register >> not entered MSCW 

aEVLK: if pseudolink = 0: 

stack_num > not ASD1/ASD2 


seg_num > not ASD1/ASD2 

aPOAV: ASD3 for client paged indexed DD is not unpaged 


aPRCW: PCW or RCW > not ASD1/ASD2 

aVOAV: ASD3 for client paged indexed DD is not unpaged 


CHES: PCW > not ASD1/ASD2 

ASD1[PCW.ASD_ref].address mod 2**13 > 0 

EXIT etc.: Stk[D{LL}+1] not RCW 


Stk[Hist-Link + 1] not {entered ENVW, inactive ENVN} 

GINX: ASD3 for paged indexed DD is not unpaged indexedDD 


GLEN: unpaged or unindexed DD > not ASD2 

ASD3 for paged indexed DD is not unpaged indexedDD 


paged indexed DD PageTable.ASD_ref > not ASD2 

MVST: Stack_number > not ASD1/ASD2 

destination Stk[0] not TSCW 

TEED & TEEU: edtab > not ASD1/ASD2 

A Structure Error is also generated during reference evaluation when: 

ASD1.address MOD 2**36 + offset > 2**36- 1 

Touch CSD CVI 1 (01) ODI 

MPCW: (sdll,sdi) >> untouched CSD 

MPWL & MPWP: SIRW or IDD >> untouched CSD 

Touch Load CVI 6 (06) ODI 

LOAD: SIRW or I1DD or ICDD >> untouched DD 

NXLN: DD[index argument] >> untouched DD 

Touch Reference CVI 5 (05) ODI 

aAPIX: PageTable[new page index] is untouched DD 

aEIXD: PageTable[page index] is untouched DD 

INDX, NXLN, 

NXLV,STOD & STON: SIRW >> untouched DD 

VALC etc.: parameter or SIRW >> untouched DD 

G–10 6878 7530–007

Undefined Operator CVI 23 (17) ODI 


This interrupt is generated for any opcode that is not defined in the current context. 

It is also generated in the following circumstances: 

EXPU: next operator is ENDE, ENDF, or INSC 

next operator is MCHR, MVNU, MINS, MFLT, 

SFSC, or SRSC (which requires source) 

EXSD & EXSU: next operator is ENDE, ENDF, or INSC 

WIPS: state identifier 5:1 true (NX68xx code) 

Unimplemented Operator OVI 3 ODI 

Unused by the Libra 680, 690, and 4000 systems processor 

6878 7530–007 G–11


Uninitialized Argument CVI 24 (18) ODI 

aPOAV, aVOAV: client argument tag in {6,4} 

ADD, AMAX & AMIN: TOS or TOS2 tag in {6,4} 

BAFP: TOS tag in {6,4} 

BCD: TOS tag in {6,4} 

BMS: length or domain tag in {6,4} 

CBON: TOS tag in {6,4} 

CHSN: TOS tag in {6,4} 

CVS2 & CV2S: x(TOS) tag in {6, 4} 

DBCD: TOS or TOS2 tag in {6,4} 

DBRS & DBST: Db tag in {6,4} 

DBUN etc.: branch-dest (TOS) tag in {6,4} 

DFTR: Len or Sb or Db tag in {6,4} 

DINS: Len or Db tag in {6,4} 

DISO: Len or Sb tag in {6,4} 

DIVD: TOS or TOS2 tag in {6,4} 

DRNT: X or L or H tag in {6,4} 

EQUL etc.: TOS or TOS2 tag in {6,4} 

EVAL, GESZ, 

GINX, GLEN: TOS tag in {6,4} 

IDIV & RDIV, 

INDX, JOIN: TOS or TOS2 tag in {6,4} 

LDNC, LDNO, 

LOAD, LODC, LODT, 

MPWL & MPWP: TOS tag in {6,4} 

MULT & MULX: TOS or TOS2 tag in {6,4} 

NORM, NORX, 

NOWR, NTGD, 

NTGR, NTIA, NTTD: TOS tag in {6,4} 

NXLN, 

NXLV, OCRX: TOS or TOS2 tag in {6,4} 

OVRD etc.: reference tag in {6,4} 

RASD etc.: TOS or TOS2 tag in {6,4} 

REMW: any argument tag in {6,4} 

RPRR: TOS tag in {6,4} 

RSQR, SESW & SEDW, 

SE8C & SE4C: TOS tag in {6,4} 

SASF etc: TOS tag in {6,4} 

SINT: TOS tag in {6,4} 

SNGL, SNGT, SPLT: TOS tag in {6,4} 

SPRR: TOS or TOS2 tag in {6,4} 

SRCH: domain tag in {6,4} 

STCD & STCN, 

STOD & STON, SUBT: TOS or TOS2 tag in {6,4} 

SXSN: TOS tag in {6,4} 

WEMW: any argument tag in {6,4} 

WTOD: TOS or TOS2 tag in {6,4} 

XTND: TOS tag in {6,4} 

G–12 6878 7530–007

Vector Arithmetic Exception OVI 2 ODI 


The following operators generate the interrupt because of arithmetic exceptions, as 

noted. Only a subset of those cases labeled "spurious" generate the interrupt. 

CPVS: RS(ND(B(i))) = TooBig [Exponent Overflow] 

RS(ND(B(i))) = TooSmall [Exponent Underflow] 

NS(RS(ND(B(i)))) = TooSmall [Exponent Underflow] 

DOT, DOTX: R(A(i)*B(i)) = TooBig [Exponent Overflow] 






POLY: R(B(i)*Z) = TooBig [Exponent Overflow] 

R(B(i)*Z) = TooSmall [Exponent Underflow] 

R(B(i)*Z) < > R*(B(i)*Z) [Precision Loss] 

N(R(B(i)*Z)) = TooSmall 



SEQ: R(Z + B(i)) = TooBig [Exponent Overflow] 

SUM & SUMA: R(sum + A(i)) = TooBig [Exponent Overflow] 

VMV: R(A(i)-B(i)) = TooBig [Exponent Overflow] 

VMVN: R(B(i)-A(i)) = TooBig [Exponent Overflow] 

VOV: R(A(i)/B(i)) = TooBig [Exponent Overflow] 

R(A(i)/B(i)) = TooSmall [Exponent Underflow] 

R(A(i)/B(i)) < > R*(A(i)/B(i)) [Precision Loss] 

N(R(A(i)/B(i))) = TooSmall 


B(i) is 0 [Divide by Zero] 

VPS: R(B(i)+S) = TooBig [Exponent Overflow] 

VPV: R(A(i)+B(i)) = TooBig [Exponent Overflow] 

VPVS: R(B(i)*S) = TooBig [Exponent Overflow] 






VSPV: R(A(i)*S) = TooBig [Exponent Overflow] 

R(A(i)*S) = TooSmall [Exponent Underflow] 

R(A(i)*S) < > R*(A(i)*S) [Precision Loss] 

N(R(A(i)*S)) = TooSmall 


R(...+B(i)) = TooBig [Exponent Overflow] 

VTS: R(B(i)*S) = TooBig [Exponent Overflow] 





VTV: R(A(i)*B(i)) = TooBig [Exponent Overflow] 





VUV: R(B(i)/A(i)) = TooBig [Exponent Overflow] 

R(B(i)/A(i)) = TooSmall [Exponent Underflow] 

R(B(i)/A(i)) < > R*(B(i)/A(i)) [Precision Loss] 

N(R(B(i)/A(i))) = TooSmall 


A(i) is 0 [Divide by Zero] 

6878 7530–007 G–13


G–14 6878 7530–007

Index 

A 

aACCE , 5-70, F-3 

aAPIX , 5-45, 

F-3 

absent code segment, 4-10, G-1 

absent data segment, 4-10, G-1 

absent segment, 4-10 

Absolute Store Reference Word (ASRW), 2-6, 

3-7 

access checking, 5-42 

access control, 2-8 

accessing segments, 2-7 

aCHAR , F-5 

activation records 

description, 2-3 

Actual Segment Descriptors (ASDs), 2-2 

actual segments, description, 2-2 

ADD , 5-20, A-1, F-14 

address couple evaluation, 5-42 

address couples, 2-3, 3-12 

CSD, 3-12 

fixed fence, 3-12 

variable fence, 3-12 

addressing, 2-1, 2-9 

current environment, 2-5 

environment, 2-9 

aEIRW , F-6 

aEIXD , F-6 

aEVCH , F-7 

aEVLK , F-7 

aFOP , 5-52, F-7 

aINTE , 4-1, F-8 

alarm interrupts, 4-22 

hardware error, 4-22 

invalid address, 4-24 

memory data error, 4-25 

alphabetical operator code list, A-1 

AMAX , 5-23, A-1, 

F-14 

AMIN , 5-23, A-1, F-14 

APIC, 6-15 

aPOAV , F-9 

approximation functions, 5-18 

aPRCW , F-11 

argument 


argument value checks, 4-17 

arithmetic exceptions, 5-10 

arithmetic interrupts, 4-7 

arithmetic overflow, 4-7 

arithmetic underflow, 4-8 

exception conditions, 4-7 

integer overflow, 4-9 

spurious interrupts, 4-7 

arithmetic operators, 5-19 

ADD, 5-20 

AMAX, 5-23 

AMIN, 5-23 

DIVD, 5-21 

IDIV, 5-21 

MULT, 5-20 

MULX, 5-21 

NORM, 5-22 

RDIV, 5-22 

SUBT, 5-20 

arithmetic overflow, 4-7, G-2 

divide by zero, 4-7 

exponent overflow, 4-7 

arithmetic underflow, 4-8, G-2 

precision loss, 4-8 

ASD 


structure errors, 4-20 

ASD memory, 2-12 

ASD Segment Types, 6-12 

ASD table, 2-12 

ASD1, 3-5 

ASD2, 3-5 

ASDs, 2-2 

ASD table, 2-12 

fields, 3-6 

memory, 2-12 

aSOP , 5-59, F-11 

ASRT , 5-73, A-1, F-14 

ASRW, 2-6, 3-7 

6878 7530–007 Index–1

Index 

assertion operators, 5-73 

ASRT, 5-73 

AVER, 5-73 

asynchronous interrupts, 4-26 

automatic page switching, 3-10 

AVER , 5-73, A-1, F-14 

aVOAV , F-12 

B 

BAFP , 6-27, 

F-14 

BCD , 5-27, A-1, 

F-14 

binary-to-decimal conversion operators, 5-27 

BCD, 5-27 

DBCD, 5-27 

binding-request token, 2-2 

bit vector interpretation, 5-29 

bit vector type transfer operators, 5-32 

evaluate word structure operators, 5-34 

literal operators, 5-31 

logical operators, 5-29 

word manipulation operators, 5-35 

bit vector type transfer operators, 5-32 

JOIN, 5-33 

SPLT, 5-32, 5-34 

STAG, 5-32 

XTND, 5-32 

bit-vector type-transfer operators 

JOIN, 5-32 

block exit, 4-11, G-2 

BMS , 5-79, A-1, F-14 

Boolean accumulators, 2-12 

Boolean Accumulators, B-1 

Boolean operands, 3-2 

bounds error, 4-14, G-3 

branching operators, 5-65 

BRFL, 5-66 

BRTR, 5-66 

BRUN, 5-66 

DBFL, 5-67 

DBUN, 5-67 

dynamic branches, 5-66 

static branches, 5-65 

BRFL , 5-66, A-1, F-15 

BRST , 5-36, A-1, F-15 

BRTR , 5-66, A-1, F-15 

BRUN , 5-66, A-2, 

F-15 

BSET , 5-36, A-2, F-15 

Byte Memory, 6-11 

Index–2 6878 7530–007 

C 

calling sequences, 4-2 

CBON , 5-34, A-2, F-15 

CEQD , 5-89, A-2, F-15 

CGED , 5-89, A-2, F-15 

CGTD , 5-89, A-2, F-15 

char_index, 3-8 

character descriptor, 3-8 

character insert operators, 5-105 

ENDF, 5-106 

INOP, 5-105 

INSC, 5-105 

INSG, 5-106 

INSU, 5-105 

MCHR, 5-106 

MFLT, 5-107 

MINS, 5-107 

MVNU, 5-107 

character move operators, 5-106 

MFLT, 5-107 

MINS, 5-107 

character reference evaluation 

operators, 5-63 

character relational operators, 5-85 

scan operators, 5-86 

SEQD, 5-86 

SEQU, 5-86 

SGED, 5-86 

SGEU, 5-86 

SGTD, 5-86 

SGTU, 5-86 

SLED, 5-86 

SLEU, 5-86 

SLSD, 5-86 

SLSU, 5-86 

SNED, 5-86 

SNEU, 5-86 

transfer operators, 5-87 

TEQD, 5-87 

TEQU, 5-87 

TGED, 5-87 

TGEU, 5-87

TGTD, 5-87 

TGTU, 5-87 

TLED, 5-87 

TLEU, 5-87 

TLSD, 5-87 

TLSU, 5-87 

TNED, 5-87 

TNEU, 5-87 

character sequence extraction operator, 5-94 

character sequence relation operators, 5-89 

character sequence relational supplant old 

comparisons, 5-90 

character set membership operators, 5-90 

scan operators, 5-90, 5-91 

SWFD, 5-91 

SWFU, 5-91 

SWTD, 5-91 

SWTU, 5-91 


TWFD, 5-92 

TWFU, 5-92 

TWTD, 5-92 

TWTU, 5-92 

character skip operators 

skip forward, 5-104 

SFDC, 5-104 

SFSC, 5-104 

skip reverse, 5-104 

SRDC, 5-104 

SRSC, 5-104 

character translate operator, 5-93 

TRNS, 5-93 

character-sequence compare operators, 5-88 

CEQD, 5-89 

CGED, 5-89 

CGTD, 5-89 

CLED, 5-89 

CLSD, 5-89 

CNED, 5-89 

CharDD, 3-8 

CHEK , 5-118, A-2, 

F-15 

CHES , 6-4, 

F-16 

CHSN , 5-39, A-2, F-16 

CLED , 5-89, A-2, F-16 

CLSD , 5-89, A-2, F-16 

CNED , 5-89, A-2, F-16 

Code Segment Descriptor (CSD), 3-9 

Code Segment Descriptors (CSDs), 2-1 

Index 

code segment dictionary, 2-4 

code segments, 2-11 

code stream 

defunct notation, 4-3 

designation, 4-3 

distribution, 5-65 

pointer, 2-11 

resumption, 4-3 

code stream pointer distribution, 5-65 

Coherent Memory, 6-11 

common actions 

aACCE, 5-70, F-3 

aAPIX, 5-45, F-3 

aCHAR, F-5 

aEIRW, F-6 

aEIXD, F-6 

aEVCH, F-7 

aEVLK, F-7 

aFOP, 5-52, F-7 

aINTE, F-8 

alphabetical listing, F-1 

aPOAV, F-9 

aPRCW, F-11 

aSOP, 5-59, F-11 

aVOAV, F-12 


computational operators, 5-8 

bit vector interpretation, 5-29 

linear index function operator, 5-39 

numeric operand interpretation, 5-8 

Condition-Vectored Interrupts (CVIs), 4-2 

consistency checks, 4-17 

control structures access rights, 2-8 

CPV , 5-111, A-2, F-16 

CPVA , 5-112, A-2, 

F-16 

CPVD , 5-112, A-2, F-16 

CPVN , 5-111, A-2, 

F-17 

CPVS , 5-112, A-2, F-17 

CREL , 5-89, 

A-2, F-17 

CSD address couples, 3-12 

CSDs, 2-1, 3-9 

untouched CSD, 3-9 

CU hardware errors, 4-24 

CV2S , 5-29, A-2, F-17 

CVIs, 4-2 

CVS2 , A-2, F-17 

CVS2 , 5-29 

6878 7530–007 Index–3

Index 

D 

data array operators, 5-77 

paged array operations, 5-77 

pointer operators, 5-80 


character sequence extraction 

operator, 5-94 

character set membership 


character translate operator, 5-93 

character-sequence compare 


decimal character sequence 


edit operators, 5-100 

unconditional character transfer 


word transfer operators, 5-99 

searching operators, 5-78 

vector operators, 5-109 

recurrence operators, 5-116 

reduction operators, 5-115 

search operators, 5-119 

vector assignment operators, 5-111 

Data Segment Descriptors (DSDs), 2-1 

data structure access, 3-20 

DDs, 3-20 

descriptors, 3-20 

operands, 3-20 


PCWs, 3-20 

primitive code, 3-20 

data structures and types, 3-1 

data type formats, D-1 

ASD1, D-4 

ASD2, D-5 

double precision/numeric, D-3 

single or double precision, Boolean 

interpretation, D-4 

single precision/ICW, D-2 

data word, 3-2 

DBCD , 5-27, A-2, F-17 

DBFL , 5-67, A-2, 

F-17 

DBRS , 5-36, A-2, F-17 

DBST , 5-36, A-3, F-18 

DBTR , 5-67, A-3, F-18 

DBUN , 5-67, 

A-3, F-18 

DCU hardware errors, 4-24 

DDs 


decimal character sequence operators, 5-94 

input convert operators, 5-98 

pack operators, 5-95 

unpack operators, 5-96 

unpack signed operators, 5-97 

unpack unsigned operators, 5-97 

decimal sequence operands, 3-4 

defined hardware error codes, 4-23 

descriptor, 2-1 

descriptor attribute extraction operators, 5-51 

GESZ, 5-52 

GINX, 5-52 

GLEN, 5-51 

descriptor interpretation, 5-7 

descriptors 


destination argument, 5-82 

destination boundary, 4-15, G-3 

Destination Boundary 

lengthening destination segment, 4-15 

Destination ID (Dest ID), 6-17 

DEXI , 5-75, A-3, 

F-18 

DFTR , 5-39, A-3, 

F-18 

diagrams, reading, 5-6 

digit sequence, 3-4 

DINS , 5-38, A-3, F-18 

DISO , 5-37, A-3, F-18 

display register, 2-5 

DIVD , 5-21, A-3, F-18 

Divide by Zero, 4-8 

DLET , 5-73, A-3, F-19 

DOT , 5-116, 

A-3, F-19 

DOTX , 5-116, A-3, F-19 

double precision floating point, 3-3 

double precision operands, 3-2 

double_integer 

magnitude, 3-4 

DoubleDD, 3-8 

DRNT , 5-24, A-3, F-19 

DSDs, 2-1 

DUPL , 5-74, A-3, 

F-19 

dyadic operators, 5-19 

dyadic vector operators, 5-111 

CPV, 5-111 

CPVA, 5-112 

CPVD, 5-112 

Index–4 6878 7530–007

CPVN, 5-111 

CPVS, 5-112 

VMV, 5-112 

VMVN, 5-112 

VOV, 5-112 

VPV, 5-112 

VTV, 5-112 

VUV, 5-112 

dyadic vector operators with scalar, 5-112 

VPS, 5-113 

VPVS, 5-113 

VSPV, 5-113 

VTS, 5-113 

dynamic branches, 5-66 

DBFL, 5-67 

DBUN, 5-67 

dynamic chain, 2-6 

E 

edit mode, 5-100 

edit mode operators, 5-103, C-1 

character insert operators, 5-105 

character move operators, 5-106 

character skip operators, 5-104 


Edit Mode Operators, C-6 

edit modes, C-1 

edit op code, 5-2 


character skip operators, 5-104 

edit mode operators, 5-103 

enter-edit operators, 5-100 

enter-single-edit operators, 5-102 

enter-table-edit operators, 5-100 

miscellaneous edit operators, 5-108 

EEXI , 5-75, A-3, 

F-19 

element_size conventions, 5-80 

E-mode Memory, 6-11 

emulation consistency error, 4-22, G-4 

emulation error, 4-22 

emulation error - here, 4-22, G-4 

emulation error - lost, 4-22, G-4 

ENDE , 5-108, A-3, F-19 

ENDF , 5-106, A-3, F-19 

enforcement interrupts, 4-14 

bounds error, 4-14 

destination boundary, 4-15 

false assertion, 4-16 

invalid access, 4-16 

invalid argument or parameter, 4-16 

invalid code word, 4-17 

invalid operator, 4-18 

invalid target, 4-18 

scratch pad error, 4-19 

source boundary, 4-18 

stack underflow, 4-19 

structure error, 4-19 

ASD, 4-19 

page, 4-19 

stack, 4-19 

undefined operator, 4-21 

Unimplemented Operator, 4-12 

uninitialized argument, 4-21 

enforcing segment boundaries, 2-7 

enter edit operators, 5-100 

enter table edit operator 

EXPU, 5-2 

EXSD, 5-2 

EXSU, 5-2 

TEED, 5-2 

TEEU, 5-2 

enter-edit operators 

enter single-edit operators, 5-102 

EXPU, 5-103 

EXSD, 5-102 

EXSU, 5-103 

enter table-edit operators, 5-100 

TEED, 5-101 

TEEU, 5-102 

single edit mode, 5-100 

table edit mode, 5-100 

enter-single-edit operators, 5-102 

enter-table-edit operators, 5-100 

ENTR , 5-69, A-3, F-20 

entry points, 4-28 

environment link, 2-5 


elements, 2-5 

fields, 3-13 

pseudo, 2-5 

pseudolink, 3-13 

environment link evaluation, 5-41 

Environment Word (ENVW), 3-15 

environmental chain, 2-5 

EQUL , 5-23, A-3, F-20 

EU hardware errors, 4-23 

EVAL , 5-57, A-3, F-20 

evaluate word structure operators, 5-34 

CBON, 5-34 

LOG2, 5-35 

RTAG, 5-34 

Index 

6878 7530–007 Index–5

Index 

EXCH , 5-74, A-3, 

F-20 

executable code stream, 2-11 

EXIT , 5-71, A-3, F-20 

exponent overflow, 4-7 

exponent underflow, 4-7 

expression stack control, 5-5 

EXPU , 5-103, A-3, F-20 

EXSD , 5-102, A-3, F-21 

EXSU , 5-103, A-3, F-21 

EXTB , 6-19, F-21 

extended address couples, 3-12 

external interrupts, 4-27 

External Memory, 6-11 

External Memory Access, 6-12 

external memory write error, 4-22 

EXTF , B-2 

F 

false assertion, 4-16, G-4 

field specifications, 3-1 

fixed fence address couples, 3-12 

FLTF, B-3 

FLTF , B-2 

FLTR , 5-38, A-4, F-21 

FMN , 5-120, A-4, F-21 

FMX , 5-120, A-4, F-21 

FMXA , 5-120, A-4, F-21 

G 

GASF , 6-28, A-4, F-21 

GASP , 6-28, A-4, F-21 

GATH , 5-114, A-4, F-22 

GESZ , 5-52, A-4, F-22 

GEXT , 6-29, A-4, F-22 

GINX , 5-52, A-4, F-22 

GLEN , 5-51, A-4, F-22 

GREQ , 5-23, A-4, 

F-22 

GRTR , 5-23, A-4, F-22 

GSTN , 6-29, A-4, F-22 

Index–6 6878 7530–007 

H 

HALT , 6-4, A-4, 

F-22 

hard POW, 3-18 

hardware error, 4-22 

hardware error - here, 4-22, G-4 

hardware error - lost, 4-23, G-4 

hidden state 

program restrictions, 6-3 

programrestrictions, 5-122 

historical chain, 2-5 

history links, 2-5 

History Word (HISW), 3-15 

HISW, 3-16 

block_exit bit, 3-16 

I 

I1DD, 3-9 

I2DD, 3-9 

ICDD, 3-9 

ICLD , 5-98, A-4, F-23 

ICR , 6-17 

ICRD , 5-98, A-4, F-23 

ICUD , 5-98, 

A-4, F-23 

ICVD , 5-98, A-4, F-23 

IDIV , 5-21, A-4, F-23 

IDLE , 6-9, A-4, F-23 

IMKS , 5-68, A-4, F-23 

IMR , 6-16 

indexed copy DD, 2-6 

IndexedCharDD, 3-9 

index field, 3-9 

char_index, 3-9 

word_index, 3-9 

IndexedDD (Indexed Data Descriptor), 3-8 

IndexedDoubleDD, 3-9 

IndexedSingleDD, 3-9 

IndexedWordDD, 3-9 

index field, 3-9 

IndexedWordDD evaluation, 5-42 

access checking, 5-42 

INDX , 5-47, A-4, F-23 

initialization error 

superhalt, 4-1 

INOP , 5-105, A-4, F-24 

input convert operators, 5-98

ICLD, 5-98 

ICRD, 5-98 

ICUD, 5-98 

INSC , 5-105, A-4, F-24 

INSG , 5-106, A-5, F-24 

INSR , 5-37, A-5, F-24 

INSU , 5-105, A-5, F-24 

integer magnitude checks, 4-17 

integer overflow, 4-7, 4-9, G-4 

integerize with rounding, 5-14 

Inter-Processor Interrupts, 6-17 

interrupt conditions, 4-2 

interrupt definition 


interrupt definitions, 4-6 

types, 4-6 

interrupt formats, 4-2 

POI, 4-2 

ROI, 4-3 

interrupt parameters, 4-4 

Interrupt Reference, G-1 

Interrupt Routing, 6-16 

interrupt slot, 4-2 

interrupt vector, 4-2, 4-29 

Interrupt Vectors, 6-15 

interrupts, 4-1, 5-3, G-2 

absent data segment, G-1 

arithmetic overflow, G-2 

arithmetic underflow, G-2 

block exit, G-2 

bounds error, G-3 

destination boundary, G-3 

false assertion, G-4 

hardware error - here, G-4 

hardware error - lost, G-4 

invalid 

address - here, G-5 

address - lost, G-5 

argument/parameter, G-5 

code word, G-7 

operator, G-7 

target, G-8 

invalid access, G-4 

loop timer - here, G-8 

loop timer - lost, G-8 

memory data error, G-8 

missing PCW, G-8 

operator-dependent ODI, 4-1 

source boundary, G-9 

spontaneous, 4-1 

stack overflow, G-9 

stack underflow, G-9 

structure error, G-10 

touch CSD, G-10 

touch load, G-10 

touch reference, G-10 

undefined operator, G-11 

uninitialized argument, G-12 

vector arithmetic exception, G-13 

invalid 

access, 4-16 

address, 4-24 

address - here, G-5 

address - lost, G-5 

argument value checks, 4-17 

argument/parameter, 4-16, G-5 

consistency checks, 4-17 

integer magnitude checks, 4-17 

invalid address, 4-24 

invalid address - Lost, 4-25 

reindex checks, 4-17 

spontaneous, 4-1 

type checks, 4-16 

invalid access, G-4 

Invalid Address Detection, 6-14 

invalid code word, 4-17, G-7 

invalid operator, 4-18, 5-121, G-7 

invalid target, 4-18, G-8 

invariants, operators, 5-3 

IPI Mode Flag Format, 6-17 

IPST , 6-4, A-5, F-24 

IRR , 6-16 

IRW chain, 5-43 

ISOL , 5-37, A-5, F-24 

item 


IWDD, 3-9 

Index 

6878 7530–007 Index–7 

J 

JOIN , 5-33, 

A-5, F-24 

L 

LAND , 5-30, A-5, F-24 

LDNC , A-5, E-1, F-24 

LDNO , A-5, E-1, 

F-25 

length argument, 5-81 

lengthening destination segment, 4-15 

LEQV , 5-30, A-5, F-25 

LESS , 5-23, A-5, F-25

Index 

lex level 


LID , 6-17 

linear index function operator 

OCRX, 5-39 

linear sum operators, 5-115 

SUM, 5-115 

SUMA, 5-115 

literal operators, 5-31 

LT16, 5-31 

LT48, 5-31 

LT8, 5-31 

ONE, 5-31 

ZERO, 5-31 

LNMC , 5-45, A-5, F-25 

LNOT , 5-30, A-5, F-25 

LOAD , 5-58, A-5, F-25 

Local APIC Registers, 6-16 

LODC , 5-63, A-5, F-25 

LODT , 5-58, A-5, F-25 

LOG2 , 5-35, A-5, F-25 

logical equality, 5-30 

logical operators, 5-29 

LAND, 5-30 

LEQV, 5-30 

LNOT, 5-30 

LOR, 5-30 

SAME, 5-30 

loop timer - here, 4-25, G-8 

loop timer - lost, 4-25, G-8 

LOR , 5-30, A-5, F-26 

LSEQ , 5-23, A-5, F-26 

LT16 , 5-31, A-5, F-26 

LT48 , 5-31, A-5, F-26 

LT8 , 5-31, A-5, F-26 

LVLC , 5-54, A-5, F-26 

M 

Machine Time of Day, 6-22 

mantissa field, 3-3 

maskable external interrupts, 4-28 

Maskable Interrupt Request, 6-18 

mathematical function operator 

RSQR, 5-28 

MaxInx, 3-10 

MaxLen, 3-10 

MCHR , 5-106, A-5, F-26 

memory data error - here, 4-25, G-8 

memory data error - lost, 4-25, G-8 

memory word, 2-12 

MFLT , 5-107, A-5, A-6, 

F-26 

MINS , 5-107, A-6, F-26 

miscellaneous edit operators, 5-108 

ENDE, 5-108 

RSTF, 5-108 

miscellaneous operators, 5-121 

NOOP, 5-121 

NVLD, 5-121 

PUSH, 5-121 

VARI, 5-121 

missing PCW, 4-11, G-8 

MKSN , 

5-68, A-6, F-26 

MKST , 5-67, A-6, F-26 

modified capability architecture 


MPCW , 5-49, A-6, F-26 

MPWL , 5-49, A-6, F-27 

MPWP , 5-49, A-6, F-27 

MPWx , 5-49 

MULT , 5-20, A-6, F-27 

multiprocessing, 2-4 

multiprogramming, 2-4 

MULX , 5-21, A-6, F-27 

MVNU , 5-107, A-6, F-27 

MVST , 6-8, F-27 

Index–8 6878 7530–007 

N 

NAMC , 5-44, A-6, F-27 

NEQL , 5-23, A-6, F-27 

NMC0 , 5-45, A-6, F-27 

NMC1 , 5-45, A-6, F-27 

NMC2 , 5-45, A-6, F-28 

NMC3 , 5-45, A-6, F-28 

Non-coherent Byte Memory, 6-11 

Non-coherent I/O, 6-11 

nondigit, 5-95 

Non-maskable Interrupt Request, 6-18 

NOOP , 5-121, A-6, F-28 

NORM , 5-22, A-6, F-28 

normal store operators, 5-59 

aSOP, 5-59 

STOD, 5-60 

STON, 5-60 

normalization function N, 5-17 

normalized values, 5-9 

NORX , 5-51, A-6, F-28

NOWR , 5-51, A-6, 

F-28 

NTGD , 5-26, A-7, F-28 

NTGR , 5-24, A-7, F-28 

NTIA , 5-25, A-7, F-28 

NTTD , 5-26, A-7, F-29 

numeric interpretation operators, 5-19 

arithmetic operators, 5-19 

binary-to-decimal conversion 


numeric relational operators, 5-23 

numeric type transfer operators, 5-24 

range test operators, 5-24 

numeric operand interpretation, 5-8 

representable values, 5-8 

numeric relational operators, 5-23 

EQUL, 5-23 

GREQ, 5-23 

GRTR, 5-23 

LESS, 5-23 

LSEQ, 5-23 

NEQL, 5-23 

numeric type transfer operators, 5-24 

NTGD, 5-26 

NTGR, 5-24 

NTIA, 5-25 

NTTD, 5-26 

SNGL, 5-25 

SNGT, 5-25 

NVLD , 5-121, A-7, F-29 

NXLN , 5-56, A-7, 

F-29 

NXLV , 5-55, A-7, F-29 

O 

obsolete operators, 5-4 

OCRX , 5-39, A-7, F-30 

ODI, 4-1 

resumable, 4-3 

OFFF , B-2 

ONE , 5-31, A-7, F-30 

op code, 5-1 

op codes 

edit, 5-2 

primary, 5-2 

variant, 5-2 

operands, 3-2 


Index 

double precision, 3-2 

real numeric, 3-3 

single precision, 3-2 

operator and common action reference, F-1 

operator applicability, 5-4 

operator encoding, C-1 

interpreting one-syllable op code, C-1 

edit mode, C-1 

primary modem, C-1 

variant, C-1 

operator subdivision, 4-5 

Operator-dependent interrupts (ODIs), 4-1 


classes, 5-4 

obsolete, 5-4 

partially restricted, 5-4 

restricted, 5-4 

unrestricted, 5-4 


order of execution, 5-2 

overwrite, 5-61 

operators and code streams, 5-1 

Operator-Vectored Interrupts (OVIs), 4-2 

other synchronous hardware errors, 4-24 

overlapping source and destination, 5-82 

overwrite operators, 5-61 

OVRD, 5-62 

OVRN, 5-62 

RDLK, 5-62 

OVRD , 5-62, A-7, F-30 

OVRN , 5-62, A-7, 

F-30 

6878 7530–007 Index–9 

P 

pack operators, 5-95 

PKLD, 5-95 

PKRD, 5-95 

PKUD, 5-95 

page boundary interrupt, 5-77 

Page Structure errors, 4-19 

page table, 3-10 

ASD_ref, 3-9 

paged array operations, 5-77 

paged virtual segment, 3-10 

page table, 3-10 

paged virtual segments 

MaxInx, 3-10 

MaxLen, 3-10 

parameter, description, 5-1 

Partitioning of Logical Memory, 6-13

Index 

PAUS , 6-9, A-7, F-30 

PCW, 2-4 

code stream pointer, 3-14 



evaluation, 5-43 

skeleton, 3-15 

PCW evaluation, 5-43 

PKLD , 5-95, A-7, 

F-30 

PKRD , 5-95, A-7, 

F-30 

PKUD , 5-95, A-7, 

F-30 

POI, 4-2 

pointer, 5-80 

pointer index restrictions, 5-108 

pointer operators, 5-80 


scan operators, 5-86 


character sequence extraction 

operator, 5-94 

character set membership operators, 5-90 

character-sequence compare 


decimal character sequence 


input convert operators, 5-98 

unpack operators, 5-96 

delete variation, 5-83 

destination arguments, 5-80 


edit mode operators, 5-103 

enter edit operators, 5-100 

element_size conventions, 5-80 

length argument, 5-81 

overlapping source and destination, 5-82 

pointer index restrictions, 5-108 

segment boundary, 5-81 

short source operators, 5-82 

source1 and source2 arguments, 5-82 

update variation, 5-83 


POLY , 5-117, A-7, 

F-31 

POW 

forms, 3-18 

precision loss, 4-7 

preconditions 


primary mode, C-1 

operator, C-1 

primary op code, 5-2 

primitive code 


procedure 


entry, 2-10 

accidental, 2-10 

explicit, 2-10 

implicit, 2-10 

procedure entry operators, 5-67 

aACCE, 5-70 

ENTR, 5-69 

IMKS, 5-68 

MKSN, 5-68 

MKST, 5-67 

procedure entry/exit, 2-9 

procedure exit operators, 5-71 

EXIT, 5-71 

RETN, 5-72 

RTN2, 5-72 

process 

creation, 2-4 


process model, 2-1 

process stack, 3-15 

processes 

stack, 2-4 

processor register, 2-5 

processor state operators, 5-65 

assertion operators, 5-73 

branching operators, 5-65 

code stream pointer distribution, 5-65 

processor-state manipulation 


stack frame operators, 5-67 


top-of-stack operators, 5-73 

processor-state manipulation operators, 5-75 

DEXI, 5-75 

EEXI, 5-75 

ROFF, 5-75 

RPRR, 6-5 

RSNR, 5-76 

RTFF, 5-75 

SXSN, 5-76 

program 


program code words, 2-11, 3-5 

syllables, 2-11, 3-5 

Program Control Word (PCW), 2-4 

program restrictions, 5-122, 6-3 

Program Segment Number (PSN), 2-11 

Program Syllable Index (PSI), 2-11 

Index–10 6878 7530–007

Program Word Index (PWI), 2-11 

Programmed Operator Interrupt (POI), 4-2 

Protected Object Words (POWs), 3-18 

protection, 2-7 

protection mechanisms, 2-7 

pseudo activation records, 3-13 

PSN, 2-11 

PUSH , 5-121, A-7, F-31 

Q 

quadratic sum operators, 5-115 

DOT, 5-116 

DOTX, 5-116 

R 

range test operators, 5-24 

DRNT, 5-24 

RASD , 6-1, A-7, F-31 

RCMT , 6-10, A-7, F-31 

RCW, 2-5, 3-15 

RDIV , 5-22, A-7, F-31 

RDLK , 5-62, A-7, F-31 

RDMT , 6-10, A-7, F-31 

read evaluation operators, 5-52 

aFOP, 5-52 

EVAL, 5-57 

LOAD, 5-58 

LODT, 5-58 

LVLC, 5-54 

NXLN, 5-56 

NXLV, 5-55 

VALC, 5-53 

real numeric operands, 3-3 

mantissa field, 3-3 

Real Time of Day, 6-21 


CHEK, 5-118 

POLY, 5-117 

SEQ, 5-116 


linear sum operators, 5-115 

SUM, 5-115 

SUMA, 5-115 

quadratic sum operators, 5-115 

DOT, 5-116 

Index 

DOTX, 5-116 

reference chains, 5-43 

chaining rule 

notation, 5-43 

IRW chain, 5-43 

SIRW chain, 5-43 

reference evaluation, 5-54 

address couple evaluation, 5-42 

IndexedWordDD evaluation, 5-55 

PCW evaluation, 5-43 

reference chains, 5-43 

SIRW evaluation, 5-42 

reference generation and evaluation 


reference generation operators, 5-44 

aAPIX, 5-45 

INDX, 5-47 

LNMC, 5-45 

MPCW, 5-49 

NAMC, 5-44 

STFF, 5-45 

reference modification operators, 5-50 

NORX, 5-51 

NOWR, 5-51 

SEsz, 5-50 

reference generation operators, 5-44 

reference modification operators, 5-50 

reference types, 3-12 

activation records, 3-13 

address couples, 3-12 

variable fence, 3-12 

CSD address couples, 3-12 

environment links, 3-13 

fixed fence address couples, 3-12 

PCWs, 3-14 

references, 2-6 

registers 

values, 2-12 

reindex bit, 3-9 

reindex checks, 4-17 

REMW , 6-14, 

A-7, F-32 

representable values, 5-8 

normalized values, 5-9 

restart configuration, 4-5 

restart mode, 4-5, 5-3 


Restartable Operator Interrupt (ROI), 4-2 

restricted operators, 5-4 

HALT, 6-4 

RASD, 6-1 

REXI, 6-5 

STOP, 6-6 

6878 7530–007 Index–11

Index 

TWOD, 6-2 

WASD, 6-2 

WATI, 6-7 

WHOI, 6-7 

WTOD, 6-10 

restrictions due to hidden state, 5-122, 6-3 

RETN , 5-72, A-7, F-32 

Return Control Word (RCW), 2-5, 3-15 

REXI , 6-5, A-8, 

F-32 

RIPS , 6-9, A-8, F-32 

RIRR , 6-19, 

A-8, F-32 

RMTR , A-8, E-2, F-32 

ROFF , 

5-75, A-8, F-32 

ROI, 4-3 

P2 parameter, 4-4 

rounding function 

Rai, 5-14 

rounding function R, 5-11 

rounding functions, 5-12 

R, example, 5-12 

RaI, 5-14 

Ri, 5-13 

RI, 5-13 

RId, 5-13 

RPRR , 6-5, A-8, 

F-32 

RREG , 6-20, A-8, F-32 

RSDN , 5-75, A-8, F-32 

RSNR , 5-76, A-8, F-32 

RSQR , 5-28, A-8, F-33 

RSTF , 5-108, A-8, F-33 

RSUP , 5-74, A-8, F-33 

RTAG , 5-34, A-8, F-33 

RTFF , 5-75, A-8, 

F-33 

RTN2 , 5-71, 5-72, A-8, 

F-33 

RTOD , 5-76, 

A-8, F-33 

RUNI , A-8, F-33 

RUNI , 6-9 

S 

SAME , 5-30, A-8, F-33 

SASF , 6-28, A-8, F-33 

SASP , 6-29, A-8, F-33 

scalars, 5-109 

SCAT , 5-114, A-8, F-34 

scatter/gather operators, 5-113 

GATH, 5-114 

SCAT, 5-114 

SCMP , 5-90, A-8, F-34 

SCPY , 5-88, A-8, F-34 

scratch pad errors, 4-19 

SCRD , A-8, E-2 

SE4C , 5-50, A-8, F-35 

SE8C , 5-50, A-9, F-35 


FMN, 5-120 

FMX, 5-120 

FMXA, 5-120 

searching operators, 5-78 

BMS, 5-78 

SRCH, 5-78 

SEDW , 5-50, A-9, F-34 

segment 

actual, 2-2 

segment boundary, 5-81 

segments 

code, 2-11 

description, 2-1, 2-12 

virtual, 2-2 

SEQ , 5-116, A-9, 

F-34 

SEQD , 5-86, A-9, 

F-34 

SEQU , 5-86, A-9, 

F-34 

service interrupts, 4-10 

absent code segment, 4-10 

absent data segment, 4-10 

absent segment, 4-10 

block exit, 4-11 

missing PCW, 4-11 

stack overflow, 4-11 

touch, 4-11 

vector arithmetic exception, 4-13 

service request, 5-44 

SESW , 5-50, A-9, F-35 

SEsz , 5-50 

SE4C , 5-50 

SEDW , 5-50 

SESW , 5-50 

Index–12 6878 7530–007

SEXT , 6-30, A-9, F-35 

SFDC , 5-104, A-9, F-35 

SFSC , 5-104, A-9, F-35 

SGED , 5-86, A-9, F-35 

SGEU , 5-86, A-9, F-35 

SGTD , 5-86, A-9, 

F-35 

SGTU , 5-86, 

A-9, F-36 

short destination operators, 5-97 

short source operators, 5-82 

SI, 4-1 

resumable, 4-3 

single edit mode, 5-100 

single precision floating point operand, 3-3 

single precision operands, 3-2 

single precision/numeric, D-1 

single_integer 

magnitude, 3-3 

SingleDD, 3-8 

SINT , 6-9, A-9, F-36 

SIRW, 2-6 


evaluation, 5-42 

SIRWs 

chain, 5-43 

SISO , 5-94, A-9, F-36 

skip forward, 5-104 

SFDC, 5-104 

SFSC, 5-104 

skip reverse, 5-104 

SRDC, 5-104 

SRSC, 5-104 

SLC interface error, 4-26 

SLC interface error - here, 4-26 

SLC interface error - lost, 4-26 

SLED , 5-86, A-9, F-36 

SLEU , 5-86, A-9, F-36 

SLSD , 5-86, A-9, 

F-36 

SLSU , 5-86, A-10, 

F-36 

SNED , 5-86, 

A-10, F-36 

SNEU , 5-86, 

A-10, F-36 

Index 

SNGL , 5-25, A-10, F-36 

SNGT , 5-25, A-10, F-37 

soft POW, 3-18 

source 


source argument, 5-81 

source boundary, 4-18, G-9 

source1 and source2 arguments, 5-82 

SPLT , 5-34, 

A-10, F-37 

spontaneous interrupt (SI), 4-1 

SPRR , 6-5, A-10, 

F-37 

spurious interrupts, 4-7 

SRCH , 5-78, 

A-10, F-37 

SRDC , 5-104, A-10, F-37 

SRSC , 5-104, A-10, F-37 

SSTN , 6-29, A-10, F-38 

stack and display registers, 2-11 

stack frame linkage, 3-16 

TSCW, 3-15 

stack frame operators, 5-67 


procedure exit operators, 5-71 

stack overflow, 4-11, G-9 

stack references, 5-41 

stack structure, 3-15 

stack structure errors, 4-19 

stack underflow, 4-19, G-9 

stacks 


expression 

current, 2-10 

frame, 2-5, 2-10 

stack-state transformation, 5-6 

STAG , 5-32, A-10, F-38 

Startup Request, 6-18 

static branches, 5-65 

BRFL, 5-66 

BRTR, 5-66 

BRUN, 5-66 

static chain, 2-6 

STCD , 5-64, A-10, 

F-38 

STCN , 5-64, 

A-10, F-38 

STFF , 5-45, A-10, F-38 

STOD , 5-60, A-10, F-38 

6878 7530–007 Index–13

Index 

STON , 5-60, A-10, F-38 

STOP , 6-6, 

A-10, F-38 

strides, 5-110 

structure error, 4-19, G-10 

ASD structure errors, 4-20 

page structure errors, 4-20 

scratch pad errors, 4-21 

stack structure errors, 4-19 

types, 4-19 

Stuffed Indirect Reference Word (SIRW), 2-6, 

3-14 

SUBT , 5-20, A-10, F-39 

SUM , 5-115, A-10, 

F-39 

SUMA , 5-115, A-11, F-39 

SUMW , 5-118, A-11, F-39 

superhalt, 4-1 

SWFD , 5-91, A-11, 

F-39 

SWFU , 5-91, A-11, 

F-39 

SWTD , 5-91, A-11, 

F-39 

SWTU , 5-91, A-11, 

F-39 

SXSN , 5-76, 

A-11, F-40 

Synchronization, 6-22 

T 

table edit mode, 5-100 

tag values, 3-19 

RTAG, 3-19 

STAG, 3-19 

Tag-4 word, 3-5 

Tag-6 word, 3-5 

TEED , 5-101, A-11, 

F-40 

TEEU , 5-102, A-11, 

F-40 

TEQD , 5-87, 

A-11, F-40 

TEQU , 5-87, 

A-11, F-40 

TFFF , B-1 

TFFF, OFFF, and EXTF, B-3 

TGED , 5-87, A-11, F-40 

TGEU , 5-87, A-11, F-40 

TGTD , 5-87, 

A-11, F-40 

TGTU , 5-87, 

A-11, F-40 

thunk, 2-10 

TI function, 5-16 

TId function, 5-16 

TLED , 5-87, A-11, F-41 

TLEU , 5-87, A-11, F-41 

TLSD , 5-87, 

A-11, F-41 

TLSU , 5-87, 

A-11, F-41 

TNED , 5-87, A-12, F-41 

TNEU , 5-87, A-12, F-41 

Top of Stack Control Word (TSCW), 3-15 

top-of-stack linkage, 3-17 

top-of-stack operators, 5-73 

DLET, 5-73 

DUPL, 5-74 

EXCH, 5-74 

RSDN, 5-75 

RSUP, 5-74 

top-of-stack pop operations, 5-6 

top-of-stack push operations, 5-5 

touch, 4-11 

Touch 

touch CSD, G-10 

touch load, G-10 

touch reference, G-10 

touch CSD, 4-12 

touch load, 4-12 

touch reference, 4-12 

touched CSD, 3-8 

untouched CSD, D-6 

TRNS , 5-93, A-12, F-41 

truncate-to-integer, 5-16 

truncation function 

T, 5-15 

Ti, 5-16 

truncation functions, 5-15 

TI, 5-16 

TId, 5-16 

TS, 5-15 

TSCW, 3-15 

Index–14 6878 7530–007

TUND , 5-84, A-12, F-41 

TUNU , 5-85, A-12, F-41 

TWFD , 5-92, 

A-12, F-42 

TWFU , 5-92, 

A-12, F-42 

TWOD , 6-2, A-12, F-42 

TWSD , 5-99, A-12, 

F-42 

TWSU , 5-99, A-12, 

F-42 

TWTD , 5-92, 

A-12, F-42 

TWTU , 5-92, 

A-12, F-42 

type checks, 4-16 

U 

unconditional character-transfer 


TUND, 5-84 

TUNU, 5-85 

undefined operator, 4-21, G-11 

unimplemented operator, 4-12, G-11 

Unimplemented Operator 

Operator Emulation, 4-12 

unindexed copy DD, 2-6 

unindexed DD, 3-8 

uninitialized argument, 4-21, G-12 

uninitialized single datum, 3-5 

unpack operators 

unpack signed operators 

UPLD, 5-97 

UPLU, 5-97 

UPND, 5-97 

UPNU, 5-97 

UPRD, 5-97 

UPRU, 5-97 

unpack unsigned operators 

UPUD, 5-97 

UPUU, 5-97 

unpaged virtual segment, 3-10 

unrestricted operators, 5-4 

untouched CSD, 3-9 

untouched DD, 3-7 

untouched original, 2-2 

untouched VSD, 3-7 

Index 

update, 5-83 

UPLD , 5-97, 

A-12, F-43 

UPLU , 5-97, 

A-12, F-43 

UPRD , 5-97, 

A-12, F-43 

UPRU , 5-97, 

A-12, F-43 

UPUD , 5-97, A-12, 

F-43 

UPUU , 5-97, 

A-12, F-43 

USND , 5-97, A-12, 

F-43 

USNU , 5-97, A-12, 

F-43 

6878 7530–007 Index–15 

V 

VALC , 5-53, A-13, F-43 

VARI , 5-121, 

A-13, F-43 

variable fence address couples, 3-12 

variant mode, C-1 

variant op codes, 5-2 

vector access, 5-110 

vector arguments, 5-109 

vector arithmetic exception, 4-13, 5-110, G-13 


dyadic vector operators, 5-111 

CPV, 5-111 

CPVA, 5-112 

CPVD, 5-112 

CPVN, 5-111 

CPVS, 5-112 

VMV, 5-112 

VMVN, 5-112 

VOV, 5-112 

VPV, 5-112 

VTV, 5-112 

VUV, 5-112 

dyadic vector operators with scalar, 5-112 

VPS, 5-113 

VSPV, 5-113 

VTS, 5-113 

scatter/gather operators, 5-113 

GATH, 5-114 

SCAT, 5-114 

vector length, 5-110 

vector operators, 5-109

Index 



scalars, 5-109 


strides, 5-110 

vector access, 5-110 

vector arguments, 5-109 

vector arithmetic, 5-110 


vectors, 5-109 

vectors, 5-109 

virtual index 

components, 3-11 


Virtual Segment Descriptor (VSD), 2-1, 3-7 

virtual segments 


domain, 5-78 

paged, 3-10 

MaxInx, 3-10 

MaxLen, 3-10 

unpaged, 3-10 

VLC0 , 5-54, A-13, F-43 

VLC1 , 5-54, A-13, F-44 

VLC2 , 5-54, A-13, F-44 

VLC3 , 5-54, A-13, F-44 

VMV , 5-112, A-13, 

F-44 

VMVN , 5-112, A-13, F-44 

VOV , 5-112, 

A-13, F-44 

VPS , 5-113, A-13, F-45 

VPV , 5-112, A-13, F-45 

VPVS , 5-113, A-13, F-45 

VSDs, 2-2, 3-7 

classes of, 2-2 

untouched, 2-2 

VSPV , 5-113, A-13, F-46 

VTS , 5-113, A-13, F-46 

VTV , 5-112, A-13, F-46 

VUV , 5-112, A-13, F-47 

W 

WASD , 6-2, A-13, 

F-47 

WATI , 6-7, 

A-13, F-47 

WEMW , 6-15, A-13, F-47 

WHOI , 6-7, A-13, F-47 

WIPS , 6-26 

WIPS , A-13, F-47 

WMTR , A-13, E-2, F-47 

word descriptor, 3-8 

word format, 3-1 

fields, 3-1 

word manipulation operators, 5-35 

BRST, 5-36 

BSET, 5-36 

CHSN, 5-39 

DBRS, 5-36 

DBST, 5-36 

DFTR, 5-39 

DINS, 5-38 

DISO, 5-37 

FLTR, 5-38 

INSR, 5-37 

ISOL, 5-37 


TWSD, 5-99 

TWSU, 5-99 

word_index, 3-9 

WordDD, 3-8 

words 


format, 3-1 

WREG , 6-20, A-13, 

F-47 

WTOD , 6-10, 

A-14, F-48 

Index–16 6878 7530–007 

X 

XTND , 5-32, A-14, 

F-48 

Z 

ZERO , 5-31, A-14, F-48 

ZIC , 6-7, A-14, F-48

© 2012 Unisys Corporation. 

All rights reserved. 

*68787530-007* 

6878 7530–007

Level Epsilon Architecture Support Reference Manual

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